公开(公告)号：US20090068810A1

公开(公告)日：2009-03-12

申请号：US12273517

申请日：2008-11-18

申请人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

发明人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S438/931 ,  Y10S438/933 ,  Y10S438/938

摘要： A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

摘要翻译： 制造金属氧化物半导体场效应晶体管的方法包括首先提供其上形成有栅极结构的衬底。 之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹槽。 另外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。 随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。 另外，源极/漏极层沉积在第二凹部中。 由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

公开(公告)号：US20120199849A1

公开(公告)日：2012-08-09

申请号：US13446124

申请日：2012-04-13

申请人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

发明人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

IPC分类号： H01L29/161 ,  H01L29/772

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S438/931 ,  Y10S438/933 ,  Y10S438/938

摘要： A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

摘要翻译： 制造金属氧化物半导体场效应晶体管的方法包括首先提供其上形成有栅极结构的衬底。 之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹槽。 另外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。 随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。 另外，源极/漏极层沉积在第二凹部中。 由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

公开(公告)号：US08207523B2

公开(公告)日：2012-06-26

申请号：US11308718

申请日：2006-04-26

申请人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

发明人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

IPC分类号： H01L29/06 ,  H01L31/00

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S438/931 ,  Y10S438/933 ,  Y10S438/938

摘要： A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

摘要翻译： 公开了一种制造金属氧化物半导体场效应晶体管的方法。 首先，设置形成有栅极结构的基板。 之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹部。 此外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。 随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。 另外，源极/漏极层沉积在第二凹部中。 由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

公开(公告)号：US20070254421A1

公开(公告)日：2007-11-01

申请号：US11308718

申请日：2006-04-26

申请人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

发明人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S438/931 ,  Y10S438/933 ,  Y10S438/938

摘要： A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

摘要翻译： 公开了一种制造金属氧化物半导体场效应晶体管的方法。 首先，设置形成有栅极结构的基板。 之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹部。 此外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。 随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。 另外，源极/漏极层沉积在第二凹部中。 由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

公开(公告)号：US08058133B2

公开(公告)日：2011-11-15

申请号：US12273517

申请日：2008-11-18

申请人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

发明人： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S438/931 ,  Y10S438/933 ,  Y10S438/938

摘要： A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

摘要翻译： 制造金属氧化物半导体场效应晶体管的方法包括首先提供其上形成有栅极结构的衬底。 之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹槽。 另外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。 随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。 另外，源极/漏极层沉积在第二凹部中。 由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

公开(公告)号：US20060228847A1

公开(公告)日：2006-10-12

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US07135365B2

公开(公告)日：2006-11-14

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US08362588B2

公开(公告)日：2013-01-29

申请号：US13159147

申请日：2011-06-13

申请人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

发明人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC分类号： H01L29/00 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

公开(公告)号：US07839826B2

公开(公告)日：2010-11-23

申请号：US11299429

申请日：2005-12-12

申请人： Edgardo L. Promenzio ,  Ajaykumar R. Idnani ,  Yi-Cheng Liu ,  Rajendra A. Panchal

发明人： Edgardo L. Promenzio ,  Ajaykumar R. Idnani ,  Yi-Cheng Liu ,  Rajendra A. Panchal

IPC分类号： H04W4/00

CPC分类号： H04L29/06027 ,  H04L65/1006 ,  H04L65/4007 ,  H04L67/14 ,  H04W36/14 ,  H04W76/10 ,  H04W76/22 ,  H04W80/10

摘要： During (101) a communication session for a plurality of user platforms wherein at least one of the user platforms is on hold and wherein the communication session is presently occurring in a first network and is terminable by a Session Initiation Protocol server as comprises a part of that first network, one establishes (102) in the first network a Session Initiation Protocol instance as corresponds to the communication session wherein the Session Initiation Protocol instance comprises, at least in part, session context information for the user platform that is on hold. Then, following a handoff of bearer support of the communication session from the first network to a second network, one uses (104) the Session Initiation Protocol instance to maintain the hold status of the user platform that is on hold with the Session Initiation Protocol server subsequent to the handoff such that the Session Initiation Protocol server does not terminate the communication session.

摘要翻译： 在（101）期间，用于多个用户平台的通信会话，其中至少一个用户平台处于保持状态，并且其中通信会话当前正在第一网络中发生并且可由会话发起协议服务器终止， 第一网络中，一个在第一网络中建立对应于通信会话的会话发起协议实例（102），其中会话发起协议实例至少部分地包括用于保持的用户平台的会话上下文信息。 然后，在从第一网络到第二网络的通信会话的承载支持的切换之后，使用（104）会话发起协议实例来保持与会话发起协议服务器处于保持状态的用户平台的保持状态 在切换之后，使得会话发起协议服务器不终止通信会话。

公开(公告)号：US07839174B2

公开(公告)日：2010-11-23

申请号：US12330768

申请日：2008-12-09

申请人： Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

发明人： Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

摘要翻译： 输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。 高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。 动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。 焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。 本文公开了混合电压输入/输出（I / O）缓冲器。