公开(公告)号：US4837609A

公开(公告)日：1989-06-06

申请号：US94573

申请日：1987-09-09

申请人： Michael Gurvitch ,  Roland A. Levy

发明人： Michael Gurvitch ,  Roland A. Levy

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/532 ,  H01L23/538 ,  H01L39/06

CPC分类号： H01L23/49888 ,  H01L21/76891 ,  H01L23/53285 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3011 ,  Y10S505/919 ,  Y10S505/922 ,  Y10S505/923

摘要： A semiconductor device which includes either a single semiconductor chip bearing an integrated circuit (IC) or two or more electrically interconnected semiconductor chips, is disclosed. This device includes interconnects between device components (on the same chip and/or on different chips), at least one of which includes a region of superconducting material, e.g., a region of copper oxide superconductor having a T.sub.c greater than about 77K. Significantly, to avoid undesirable interactions, at high processing temperatures, between the superconducting material and underlying, silicon-containing material (which, among other things, results in the superconducting material reverting to its non-superconducting state), the interconnect also includes a combination of material regions which prevents such interactions.

公开(公告)号：US4179802A

公开(公告)日：1979-12-25

申请号：US890445

申请日：1978-03-27

申请人： Kailash C. Joshi ,  Ronald N. Spaight

发明人： Kailash C. Joshi ,  Ronald N. Spaight

IPC分类号： H05K3/34 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/485 ,  H01L23/522 ,  H01L23/538 ,  H01L27/04 ,  H01L39/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  Y10S505/923 ,  Y10S505/927 ,  Y10T29/49126 ,  Y10T29/49149 ,  Y10T29/49156

摘要： A plurality of metal studs are plated on a chip carrier surface in a pattern to match a terminal metal footprint on a chip to be joined. The studs are of sufficient height to permit flux cleaning, if necessary. After the studs are in place, the chip is aligned with the carrier and attached thereto, the chip pads containing a small amount of solder to provide the connecting joints. The carrier and chip are made of materials having nearly equal thermal expansion characteristics.

摘要翻译： 将多个金属螺柱以图案电镀在芯片载体表面上以匹配要连接的芯片上的端子金属覆盖区。 如果需要，螺柱具有足够的高度以允许焊剂清洁。 在螺柱就位之后，芯片与载体对准并附接到其上，芯片焊盘包含少量焊料以提供连接接头。 载体和芯片由具有几乎相等的热膨胀特性的材料制成。

公开(公告)号：US4990489A

公开(公告)日：1991-02-05

申请号：US215802

申请日：1988-07-06

申请人： Yoji Mashiko ,  Tadashi Nishioka

发明人： Yoji Mashiko ,  Tadashi Nishioka

IPC分类号： H01L23/522 ,  G11C7/00 ,  G11C17/00 ,  G11C17/12 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8246 ,  H01L23/525 ,  H01L23/532 ,  H01L27/112 ,  H01L29/43 ,  H01L39/00 ,  H01L39/06 ,  H01L39/24

CPC分类号： H01L23/53285 ,  G11C17/00 ,  G11C17/12 ,  G11C7/005 ,  H01L21/76891 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10S148/046 ,  Y10S505/70 ,  Y10S505/703 ,  Y10S505/706 ,  Y10S505/831 ,  Y10S505/841 ,  Y10S505/923

摘要： A read only memory device includes a first electrode and a second electrode arranged in an overlapping relation with the first electrode so as to be geometrically in connection at an intersection therewith corresponding to a storage location for one type of data. At least one of the first and second electrodes is formed of a ceramics system high temperature superconductor. A prescribed one of the two electrodes which is formed of the high temperature superconductor has a high resistance region for insulating the first and second electrodes from each other at an intersection corresponding to a storage location for another type of stored data. The high resistance region is formed by irradiating an intersection with a focused ion beam.

摘要翻译： 只读存储器件包括第一电极和第二电极，该第一电极和第二电极以与第一电极重叠的关系布置，以便在与其对应于一种类型的数据的存储位置的交叉点几何地连接。 第一和第二电极中的至少一个由陶瓷系统的高温超导体形成。 由高温超导体形成的两个电极中规定的一个电极具有高电阻区域，用于在对应于另一类型的存储数据的存储位置的交叉点处彼此绝缘第一和第二电极。 通过照射与聚焦离子束的交点来形成高电阻区域。

公开(公告)号：US5770470A

公开(公告)日：1998-06-23

申请号：US694300

申请日：1996-08-08

申请人： Gun-Yong Sung ,  Jeong-Dae Suh

发明人： Gun-Yong Sung ,  Jeong-Dae Suh

IPC分类号： H01L39/22 ,  H01L27/18 ,  H01L39/14 ,  H01L39/24 ,  H01B12/00

CPC分类号： H01L39/146 ,  Y10S505/922 ,  Y10S505/923

摘要： The invention relates to a high temperature superconducting electric field effect device which creates a dual grain boundary on a superconducting thin film and employs it as a channel. The device comprises a substrate, a bottom layer formed on a predetermined region of the bottom layer, a dual grain boundary channel region formed on the bottom layer, a high temperature source and a drain formed at both end portions of the channel region on the substrate, a high temperature superconducting thin film channel layer formed a predetermined region on the source, the drain and the substrate, dual grain boundaries formed on the high temperature superconducting thin film channel layer, and a gate insulating layer formed on the dual grain boundary channel region.

摘要翻译： 本发明涉及一种在超导薄膜上产生双晶边界并将其用作沟道的高温超导电场效应装置。 该器件包括衬底，形成在底层的预定区域上的底层，形成在底层上的双晶界沟道区，在衬底上的沟道区的两个端部处形成的高温源和漏极 ，在源极，漏极和衬底上形成预定区域的高温超导薄膜沟道层，形成在高温超导薄膜沟道层上的双晶边界，以及形成在双晶界面区域上的栅极绝缘层 。

公开(公告)号：US4075756A

公开(公告)日：1978-02-28

申请号：US701059

申请日：1976-06-30

申请人： Charles John Kircher ,  Hans Helmut Zappe

发明人： Charles John Kircher ,  Hans Helmut Zappe

IPC分类号： H05K3/46 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/3205 ,  H01L23/522 ,  H01L39/24 ,  H05K3/00

CPC分类号： H01L21/02175 ,  H01L21/02238 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S505/923 ,  Y10T29/49156

摘要： A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level than the niobium; and the removal of the photoresist.

摘要翻译： 公开了一种用于集成电路的制造方法，其中在支撑衬底的一侧上形成一个结构，该支撑衬底的一侧提供接地平面“X”布线，而在另一侧具有“Y”布线。 该方法包括许多替代的初始平坦化步骤，其允许所得到的器件基本上是平面的，从而允许其用作制备高密度集成电路的衬底。 第一平面化步骤包括在掺杂硅衬底上沉积铌薄膜; 使用公知的光刻和蚀刻技术描绘所需的铌“X”布线图案，留下光致抗蚀剂以保护铌; 暴露的硅衬底部分的阳极氧化以形成围绕铌的二氧化硅至比铌更高的水平; 并去除光致抗蚀剂。

公开(公告)号：US3649356A

公开(公告)日：1972-03-14

申请号：US3649356D

申请日：1969-12-31

申请人： NASA

发明人： MULLEN LEWIS O ,  SULLIVAN DONALD B

IPC分类号： H01L39/24 ,  B44D1/14 ,  B44D1/18

CPC分类号： H01L39/2493 ,  Y10S505/923 ,  Y10T29/49014

摘要： A first electrical conductor body is cooled to below 100* K. in a vacuum chamber. The chamber is then pressurized with oxygen and after a period of time a glow discharge is established in the chamber. After a time the glow discharge is terminated, the chamber is evacuated and a second electrical conductor material is deposited on the first body. Both bodies are then heated to ambient temperature. As optional steps the first conductor may be heated to below 0* C. and recooled to below 100* K. before depositing the second conductor body.

摘要翻译： 在真空室中将第一导电体冷却至低于100°K。 然后用氧气对腔室进行加压，并且在一段时间之后，在室中建立辉光放电。 一段时间后，辉光放电终止，腔室被排空，并且第二电导体材料沉积在第一体上。 然后将两个体加热至环境温度。

公开(公告)号：US3383758A

公开(公告)日：1968-05-21

申请号：US53655866

申请日：1966-03-09

申请人： GEN ELECTRIC

发明人： BREMER JOHN W

IPC分类号： C23C14/04 ,  C23F1/30 ,  H01L39/24

CPC分类号： H01L39/24 ,  C23C14/04 ,  C23C14/042 ,  C23F1/30 ,  Y10S505/917 ,  Y10S505/923 ,  Y10T29/49014

公开(公告)号：US5130273A

公开(公告)日：1992-07-14

申请号：US642246

申请日：1991-01-07

申请人： Yoji Mashiko ,  Tadashi Nishioka

发明人： Yoji Mashiko ,  Tadashi Nishioka

IPC分类号： H01L23/522 ,  G11C7/00 ,  G11C17/00 ,  G11C17/12 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8246 ,  H01L23/525 ,  H01L23/532 ,  H01L27/112 ,  H01L29/43 ,  H01L39/00 ,  H01L39/06 ,  H01L39/24

CPC分类号： H01L23/53285 ,  G11C17/00 ,  G11C17/12 ,  G11C7/005 ,  H01L21/76891 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10S148/046 ,  Y10S505/70 ,  Y10S505/703 ,  Y10S505/706 ,  Y10S505/831 ,  Y10S505/841 ,  Y10S505/923

摘要： A read only memory device comprises a first electrode, and a second electrode arranged overlapping with the first electrode so as to be geometrically in connection at the intersection. At least one of the first and second electrodes is formed of a ceramics system high temperature superconductor. A prescribed electrode out of said electrodes which is formed of the high temperature superconductor has a high resistance region for insulating the first and second electrodes from each other at the intersection corresponding to a prescribed stored data.In the manufacturing method, the first and second electrodes are formed and, thereafter, a high resistance region is formed by irradiating focused ion beam.

公开(公告)号：US5084437A

公开(公告)日：1992-01-28

申请号：US486474

申请日：1990-02-28

申请人： John J. Talvacchio

发明人： John J. Talvacchio

IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L21/338 ,  H01L21/86 ,  H01L29/43 ,  H01L29/778 ,  H01L29/812 ,  H01L39/00 ,  H01L39/24

CPC分类号： H01L39/2474 ,  H01L21/86 ,  Y10S505/701 ,  Y10S505/703 ,  Y10S505/923

摘要： This is a method for making an ohmic connection between a semiconductor and oxide superconductor, the connection being such that current can pass between the semiconductor and the superconductor without going through a degraded portion which is greater than the coherence length of the superconductor. The method can comprise depositing a buffer layer (which is essentially inert to the oxide superconductor) on a first portion of a semiconductor substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer (e.g. of gold or silver) on the oxide superconductor, and depositing a semiconductor contact layer on a second portion of the semiconductor substrate (the semiconductor contact layer being, for example, of aluminum, or a refractory metal silicide); and depositing a layr (e.g. of gold or aluminum) on the semiconductor contact layer and on at least a portion of the superconductor contact layer to electrically connect the semiconductor contact laye and the superconductor contact layer. Alternately, the method can comprise depositing a buffer layer on a first portion of a substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer on the oxide superconductor, and depositing a semiconductor on a second portion of the substrate, and depositing a semiconductor contact layer on the semiconductor, and depositing a layer on the semiconductor contact layer and on at least a portion of the superconductor contact layer to electrically connect the semiconductor contact layer and the superconductor contact layer. Preferably, the superconductor contact layer is of gold, the semiconductor contact layer and the interconnecting layer are of aluminum, and the buffer layer is of zirconium oxide.

公开(公告)号：US4395813A

公开(公告)日：1983-08-02

申请号：US199163

申请日：1980-10-22

申请人： John A. Roth ,  Lynette B. Roth

发明人： John A. Roth ,  Lynette B. Roth

IPC分类号： H01L39/22 ,  H01L39/16 ,  H01L39/24

CPC分类号： H01L39/223 ,  H01L39/22 ,  Y10S505/922 ,  Y10S505/923 ,  Y10T29/49014

摘要： The specification discloses a process for forming a superconductor/semiconductor junction structure having optimized low-temperature current transport properties by first providing a substrate of a chosen semiconductor material having an atomically clean surface. A layer of a first chosen superconducting material is deposited on or above the surface of the substrate to a predetermined thickness. Either before or after the formation of this layer of the first superconducting material, a region of a second chosen superconducting material is formed between the surface of the substrate and the layer of the first superconducting material to serve as an interfacial reaction barrier to prevent the reaction between the surface of the substrate and the first chosen superconducting material at the interface thereof which would otherwise result in the formation of an undesired non-superconducting material at the interface. By preventing this undesired interfacial reaction, an optimized low-temperature current transport path is maintained across the interface and certain device performance characteristics can be optimized. Josephson junction superconducting devices and super-Schottky devices may be formed by this disclosed process.

摘要翻译： 该说明书公开了一种通过首先提供具有原子清洁表面的所选择的半导体材料的衬底来形成具有优化的低温电流传输特性的超导体/半导体结结构的方法。 将第一选择的超导材料的层沉积在基板的表面上或上方至预定厚度。 在第一超导材料的该层形成之前或之后，在基板的表面和第一超导材料层之间形成第二选择的超导材料的区域，以用作界面反应势垒以防止反应 在衬底的表面和其界面处的第一选择的超导材料之间，否则这将导致在界面处形成不需要的非超导材料。 通过防止这种不希望的界面反应，跨接口保持优化的低温电流传输路径，并且可以优化某些器件性能特性。 约瑟夫逊结超导器件和超肖特基器件可以通过该公开的工艺形成。