公开(公告)号：US10298382B2

公开(公告)日：2019-05-21

申请号：US15673298

申请日：2017-08-09

Applicant: OmniVision Technologies, Inc.

Inventor： Charles Qingle Wu ,  Qi Niu

IPC: H04L7/033 ,  H04L7/08 ,  G11B20/14 ,  H03L7/099 ,  H03L7/085 ,  G06F7/68 ,  G06F1/08 ,  H03C3/09 ,  H03L7/18

Abstract: A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

公开(公告)号：US07298811B2

公开(公告)日：2007-11-20

申请号：US11343234

申请日：2006-01-31

Applicant: Bardo Müller

Inventor： Bardo Müller

IPC: H03B19/00 ,  G06F7/68

CPC classification number: H03K23/50 ,  H03K3/2885 ,  H03K23/665

Abstract: The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a “1”, and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.

Abstract translation: 本发明公开了一种使用半加法功能的分频器，包括一个具有每个数字加半功能的锁存电路，每个锁存电路在其S输入端接收其输出信号Sout，锁存电路（76）用于最低有效位接收 在其进位输入处为“1”，并且每个进一步的锁存电路在其进位输入处接收来自前一个数字的锁存电路的进位信号，以及接收锁存电路的和输出的“和”门电路。

公开(公告)号：US20050282511A1

公开(公告)日：2005-12-22

申请号：US11153319

申请日：2005-06-16

Applicant: Mitsuaki Tagishi

Inventor： Mitsuaki Tagishi

IPC: G06F1/08 ,  G06F7/68 ,  H03K5/00 ,  H03K5/135 ,  H03K5/14 ,  H03L7/06 ,  H04B1/40

CPC classification number: H03K5/135 ,  G06F7/68 ,  H03K5/00006

Abstract: Disclosed is a frequency multiply circuit for outputting an output signal obtained by variably multiplying the frequency of an input signal includes a synchronous delay circuit, a multiplexing circuit, and a control circuit. The synchronous delay circuit includes a period measuring delay circuit for measuring the period of the input signal and delay reproducing delay circuits each with a delay time thereof variably set based on the period measured by the period measuring delay circuit, for respectively reproducing the delay time. The multiplexing circuit receives a plurality of signals of different phases output from the synchronous delay circuits, for multiplexing. The control circuit variably sets the number of the delay stages of the period measuring delay circuit and the numbers of the stages of the delay reproducing delay circuits, according to the set frequency-multiplication factor. The output signal synchronized with the input signal and obtained by multiplying the frequency of the input signal is output from the multiplexing circuit.

Abstract translation: 公开了一种频率乘法电路，用于输出通过可变地乘以包括同步延迟电路，多路复用电路和控制电路的输入信号的频率而获得的输出信号。 同步延迟电路包括用于测量输入信号的周期和延迟再现延迟电路的周期测量延迟电路，每个延迟电路具有基于由周期测量延迟电路测量的周期可变地设置的延迟时间，以分别再现延迟时间。 复用电路接收从同步延迟电路输出的不同相位的多个信号，用于多路复用。 控制电路根据设定的倍频系数可变地设定周期测量延迟电路的延迟级数和延迟再生延迟电路的级数。 与输入信号同步并通过乘以输入信号的频率获得的输出信号从复用电路输出。

公开(公告)号：US06967512B2

公开(公告)日：2005-11-22

申请号：US10330017

申请日：2002-12-26

Applicant: Minoru Kozaki

Inventor： Minoru Kozaki

IPC: G06F1/06 ,  G06F7/68 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13 ,  H03K5/15 ,  H03K19/096 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/06

CPC classification number: G06F7/68 ,  H03K3/0322 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00039 ,  H03K2005/00208

Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1′ are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS transistor N1′ are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1′ through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1′ through an inverter IV2.

Abstract translation: 在电路块BL 1中，PMOS晶体管P 1和PMOS晶体管P 1'串联连接在高电平电位HL和输出端子U 1之间; NMOS晶体管N 1和NMOS晶体管N 1'串联连接在低电平电位LL和输出端子U 1之间。 时钟信号Ck 1的反相信号Ck1B输入到PMOS晶体管P 1的栅极; 时钟信号Ck 1的反相信号Ck1B通过反相器IV 1输入到PMOS晶体管P 1'的栅极; 时钟信号Ck 2被输入到NMOS晶体管N1的栅极; 并且时钟信号Ck 2通过反相器IV 2输入到NMOS转换器N 1'的栅极。

公开(公告)号：US06958633B2

公开(公告)日：2005-10-25

申请号：US10707514

申请日：2003-12-19

Applicant: Hsiuan-Hau Chien

Inventor： Hsiuan-Hau Chien

IPC: G06F7/68 ,  H03K23/68 ,  H03K21/00

CPC classification number: G06F7/68 ,  H03K23/68

Abstract: A method includes generating N reference clocks with period T and phases uniformly distributed in 360 degrees; using each of the N reference clocks to trigger M intermediate signals with period M*T and phases uniformly distributed in 360 degrees; and performing a logic operation between at least two intermediate signals respectively corresponding to two different reference clocks to generate an output clock with period (M/N)*T to achieve non-integer frequency division.

Abstract translation: 一种方法包括产生具有周期T的N个参考时钟和以360度均匀分布的相位; 使用N个参考时钟中的每一个来触发具有周期M * T的M个中间信号，并且以360度均匀分布的相位; 并且在分别对应于两个不同参考时钟的至少两个中间信号之间执行逻辑运算，以产生具有周期（M / N）* T的输出时钟，以实现非整数分频。

公开(公告)号：US06946915B2

公开(公告)日：2005-09-20

申请号：US10656762

申请日：2003-09-08

Applicant: Xiaopin Zhang

Inventor： Xiaopin Zhang

IPC: G06F7/68 ,  H03C3/09 ,  H03L7/091 ,  H03L7/093 ,  H03L7/197 ,  H03L7/085 ,  H03C3/00 ,  H03L7/10 ,  H03L7/16 ,  H04L27/12

CPC classification number: H03L7/1974 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0991 ,  H03L7/091 ,  H03L7/093

Abstract: A fractional-N frequency synthesizer using the first order Delta-Sigma frequency discriminator which is composed of only a dual modulus frequency divider and a D flip-flop is used to replace the function of phase detector is disclosed. The invented structure is characterized by generating the feedback error signal indirectly from the output bit stream of said discriminator in such a way that the quantization noise contained in the bit stream is maximally canceled by comparing it with another bit stream generated by an accumulator digitally performing the first order Delta-Sigma modulation to the required fractional number, so that there is almost no discrete fractional spurs in the output spectrum of the synthesizer. Most other circuit of the synthesizer could be formed digitally so that high integration level and low noise performance could be achieved. Narrow or wideband phase or frequency modulation could also be conveniently added digitally with good accuracy.

Abstract translation: 使用仅由双模分频器和D触发器组成的一阶Delta-Sigma频率鉴别器的分数N频率合成器用于替代相位检测器的功能。 本发明的结构的特征在于从所述鉴频器的输出比特流间接地产生反馈误差信号，使得通过将由比特流中包含的量化噪声与由数字执行 一阶Delta-Sigma调制到所需的分数，从而在合成器的输出频谱中几乎没有离散的分数杂散。 合成器的大多数其他电路可以数字形成，从而可以实现高集成度和低噪声性能。 窄带或宽带相位或频率调制也可以以良好的精度数字方便地添加。

公开(公告)号：US20050200393A1

公开(公告)日：2005-09-15

申请号：US11074338

申请日：2005-03-07

Applicant: Wolfgang Furtner

Inventor： Wolfgang Furtner

IPC: G06F1/08 ,  G06F7/68 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/16 ,  H03L7/22

CPC classification number: G06F1/08 ,  G06F7/68 ,  H03K5/135 ,  H03L7/0812 ,  H03L7/22

Abstract: A method and device for generating a clock signal with predetermined clock signal properties firstly prepare a number of clock signals with an essentially identical frequency and with a respectively different phase relation with regard to a master clock signal in order to subsequently (on the basis of a control signal, which is prepared according to the clock signal to be generated), select predetermined clock signals from the number of prepared clock signals and to combine the selected clock signals in order to generate the desired clock signal.

Abstract translation: 一种用于产生具有预定时钟信号特性的时钟信号的方法和装置首先准备了许多具有相对于主时钟信号的基本上相同的频率和相应不同的相位关系的时钟信号，以便随后（基于 根据要生成的时钟信号准备的控制信号）从准备好的时钟信号的数量中选择预定的时钟信号，并组合所选择的时钟信号以产生所需的时钟信号。

公开(公告)号：US6134285A

公开(公告)日：2000-10-17

申请号：US864629

申请日：1997-05-28

Applicant: Wei-Chi Lo

Inventor： Wei-Chi Lo

IPC: G06F1/04 ,  G06F7/68 ,  H04L7/02 ,  H04L7/08

CPC classification number: G06F7/68 ,  G06F1/04 ,  H04L7/02 ,  H04L7/08

Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register. In some embodiments of the data receiver an integer error compensation circuit compensates for the difference between the actual number of clock periods in a data period and the integer clock period count. A divider divides the integer clock period count to calculate an integer N and causes a data register to capture a data word on the N-th occurrence of an active edge of the clock signal after the beginning of the data word.

公开(公告)号：US6107846A

公开(公告)日：2000-08-22

申请号：US965410

申请日：1997-11-06

Applicant: Nobuaki Shinmori

Inventor： Nobuaki Shinmori

IPC: G06F7/68 ,  H03K5/00 ,  H03B19/00

CPC classification number: H03K5/00006 ,  G06F7/68

Abstract: A frequency multiplication circuit generates an output clock signal having a frequency obtained by multiplying an external clock signal inputted from outside by a predetermined number. The frequency multiplication circuit circuit includes an edge detection circuit for detecting a signal edge of the external clock signal and outputting an edge detection signal, an oscillation circuit for generating and outputting a reference clock signal having a predetermined frequency, and a clock generating circuit for taking in the edge detection signal outputted by the edge detection circuit and the reference clock signal outputted by the oscillation circuit, counting the number of clocks of the reference clock signal, directly outputting the reference clock signal before the number of clocks reaches a predetermined number, outputting no reference clock signal after the number of clocks has reached the predetermined number, and resetting a process of counting the number of reference clocks when inputting the edge detection circuit.

Abstract translation: 倍频电路产生具有通过将从外部输入的外部时钟信号乘以预定数而获得的频率的输出时钟信号。 倍频电路包括用于检测外部时钟信号的信号边沿并输出边沿检测信号的边缘检测电路，用于产生和输出具有预定频率的参考时钟信号的振荡电路和用于采集的时钟产生电路 在由边缘检测电路输出的边缘检测信号和由振荡电路输出的参考时钟信号中，对基准时钟信号的时钟数进行计数，在时钟数达到预定数量之前直接输出基准时钟信号，输出 在时钟数量已经达到预定数量之后没有参考时钟信号，并且在输入边缘检测电路时复位对参考时钟数进行计数的处理。

公开(公告)号：US5914984A

公开(公告)日：1999-06-22

申请号：US898621

申请日：1997-07-22

Applicant: Mario Di Guardo ,  Giuseppe D'Angelo ,  Matteo Lo Presti

Inventor： Mario Di Guardo ,  Giuseppe D'Angelo ,  Matteo Lo Presti

IPC: G06F7/68 ,  H02M7/5395 ,  H02P27/08 ,  H03K7/08

CPC classification number: G06F7/68 ,  H02M7/5395

Abstract: In a fully digital PWM controller employing a sine-triangle modulating technique, the method includes the step of linearizing the dependence of the selected scanning frequency of the memory containing the digital samples of the modulating sinusoid, from the value of the digital selection datum, and improves regulation at low speed by improving the resolution of selectable frequency values. The PWM driving signals produced by a fully digital controller implementing the linearization step of the invention show an F.F.T. extremely close to the F.F.T. of comparable PWM driving signals produced through a conventional analog technique.

Abstract translation: 在采用正弦三角调制技术的全数字PWM控制器中，该方法包括从数字选择基准值的值线性化包含调制正弦波数字样本的存储器的选定扫描频率的依赖性的步骤，以及 通过提高可选择的频率值的分辨率来改善低速调节。 由实现本发明的线性化步骤的全数字控制器产生的PWM驱动信号显示F.F.T. 非常接近F.F.T. 通过常规模拟技术产生的可比PWM驱动信号。