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公开(公告)号：US20240347110A1
公开(公告)日：2024-10-17
申请号：US18755062
申请日：2024-06-26
发明人： Jian Huang , Zhenming Zhou
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C29/4401 , G11C2029/1202
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion, performing a write operation on the second wordline to program second data.
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公开(公告)号：US20240338215A1
公开(公告)日：2024-10-10
申请号：US18745042
申请日：2024-06-17
申请人： SK hynix Inc.
发明人： Dong Uk LEE , Seung Gyu JEONG , Dong Ha JUNG
IPC分类号： G06F9/30 , G06F9/48 , G06F12/02 , G06F12/0882 , G06F13/16 , G11C5/02 , G11C11/4093 , G11C29/42 , G11C29/44
CPC分类号： G06F9/30047 , G06F9/4818 , G06F12/0246 , G06F12/0882 , G06F13/1663 , G11C5/025 , G11C11/4093 , G11C29/42 , G11C29/44
摘要： A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.
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公开(公告)号：US12112817B2
公开(公告)日：2024-10-08
申请号：US17827997
申请日：2022-05-30
发明人： Biao Song
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/12015 , G11C29/4401 , G11C2029/3602
摘要： Embodiments relate to a test method, a computer apparatus, and a computer-readable storage medium. The test method includes: writing first data into a target memory cell; performing reverse writing on the target memory cell; reading second data stored in the target memory cell after the reverse writing; determining whether the second data are the same as the first data; and determining that write recovery time of the target memory cell fails when the second data are the same as the first data. The present disclosure can make an effective test of determining whether the write recovery time fails.
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公开(公告)号：US12100467B2
公开(公告)日：2024-09-24
申请号：US17822032
申请日：2022-08-24
CPC分类号： G11C29/789 , G11C29/027 , G11C29/24 , G11C29/4401 , G11C29/46
摘要： An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US12094551B2
公开(公告)日：2024-09-17
申请号：US17133810
申请日：2020-12-24
申请人： Intel Corporation
发明人： Hwa Chaw Law , Yu Ying Ong
CPC分类号： G11C29/42 , G11C29/1201 , G11C29/44 , G11C29/78
摘要： A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.
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公开(公告)号：US20240290412A1
公开(公告)日：2024-08-29
申请号：US18346339
申请日：2023-07-03
IPC分类号： G11C29/44 , G06F12/1009 , G11C29/12
CPC分类号： G11C29/44 , G06F12/1009 , G11C29/12005 , G11C2029/1202
摘要： As part of the erase operation for a memory block, one or more post-erase tests can be incorporated into the erase operation to see whether the block has grown any defects. After erasing a block and verifying the erase, the post-erase tests can be performed on the block. As these test involve biasing the block and performing a sensing operation, these post erase tests come with a time penalty. To reduce the associated time penalty and improve memory performance while incorporating the defect tests into the erase process, when biasing the memory array for the post-erase defect tests different ramp rates can be used. In particular, faster ramp rates for bias levels, such those applied to the word lines of the block, are used for the post-erase tests than are used for the same bias level when performing the standard read, program verify, or read verify operations.
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公开(公告)号：US20240290411A1
公开(公告)日：2024-08-29
申请号：US18597454
申请日：2024-03-06
发明人： Chun S. Yeung , Deping He , Jonathan S. Parry
CPC分类号： G11C29/42 , G11C7/04 , G11C29/1201 , G11C29/4401 , G11C2029/1202 , G11C2029/1204
摘要： Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.
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公开(公告)号：US12073217B2
公开(公告)日：2024-08-27
申请号：US18061370
申请日：2022-12-02
申请人： SK hynix Inc.
发明人： Dong Uk Lee , Seung Gyu Jeong , Dong Ha Jung
IPC分类号： G06F9/30 , G06F9/48 , G06F12/02 , G06F12/0882 , G06F13/16 , G11C5/02 , G11C11/4093 , G11C29/42 , G11C29/44
CPC分类号： G06F9/30047 , G06F9/4818 , G06F12/0246 , G06F12/0882 , G06F13/1663 , G11C5/025 , G11C11/4093 , G11C29/42 , G11C29/44
摘要： A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.
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公开(公告)号：US20240257896A1
公开(公告)日：2024-08-01
申请号：US18543687
申请日：2023-12-18
发明人： Seungki HONG , Seungjun LEE
CPC分类号： G11C29/44 , G11C29/18 , G11C2029/1802
摘要： A repair circuit, including a first fail address latch configured to latch a first fail address and a second fail address corresponding to a first bank; a second fail address latch configured to latch a third fail address and a fourth fail address corresponding to a second bank different from the first bank; a fail address multiplexer configured merge the first fail address and the third fail address into a first merge address, and to merge the second fail address and the fourth fail address into a second merge address; a comparison circuit configured to compare the first and second merge addresses with merged decoded row addresses to generate first and second hit signals; a logic operator configured to output a valid hit pre-signal based on the first and second hit signals; and a valid hit latch configured output a valid hit signal based on the valid hit pre-signal.
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公开(公告)号：US20240249792A1
公开(公告)日：2024-07-25
申请号：US18625895
申请日：2024-04-03
发明人： Yung-Huei Lee , Pei-Chun Liao , Jian-Hong Lin , Dawei Heh , Wen Hsien Kuo
CPC分类号： G11C29/4401 , G11C13/0004 , G11C13/0069 , G11C29/12005 , G11C29/38
摘要： A method of extending a lifetime of a memory cell is provided. The method includes detecting, by a memory controller, whether a memory cell has failed or not; repairing, by the memory controller, the memory cell by applying a first pulse having a first amplitude to the memory cell, in response to determining that the memory cell has failed; and writing, by the memory controller, input data to the memory cell by applying a second pulse having a second amplitude less than the first amplitude, in response to repairing the memory cell. In one expect, the detecting includes writing, by the memory controller, additional input data to the memory cell; reading, by the memory controller, data stored by the memory cell; comparing, by the memory controller, the data stored by the memory cell with the additional input data; and determining whether the memory cell has failed according to the comparison.
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