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1.发明授权公开(公告)号：US11962305B2
公开(公告)日：2024-04-16
申请号：US17303839
申请日：2021-06-09
申请人： NXP B.V.
发明人： Björn Fay
CPC分类号： H03K3/84 , G06F7/58 , G06F7/588 , H03K3/0315 , H03K21/08
摘要： A true random number generator circuit includes a ring oscillator and a plurality of sampling circuits. The ring oscillator includes a plurality of series-connected stages coupled together in a ring. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. A sampling circuit of the plurality of sampling circuits has an input coupled to a node located between two adjacent stages of the plurality of series-connected stages. Every node of the ring oscillator is coupled to a corresponding sampling circuit of the plurality of sampling circuits. In another embodiment, a method for generating a random number is provided.
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公开(公告)号：US11960854B2
公开(公告)日：2024-04-16
申请号：US17028723
申请日：2020-09-22
CPC分类号： G06F7/5443 , H03K21/08 , H03K19/20
摘要： A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.
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公开(公告)号：US20240113716A1
公开(公告)日：2024-04-04
申请号：US17956576
申请日：2022-09-29
IPC分类号： H03K21/08 , H03K17/687
CPC分类号： H03K21/08 , H03K17/6871
摘要： In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.
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公开(公告)号：US11789072B2
公开(公告)日：2023-10-17
申请号：US17947641
申请日：2022-09-19
发明人： Wei-Ling Lin
IPC分类号： H03K5/00 , G01R31/317 , H03K21/08 , H03K5/19
CPC分类号： G01R31/31727 , H03K5/19 , H03K21/08
摘要： A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.
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公开(公告)号：US11742836B1
公开(公告)日：2023-08-29
申请号：US17659211
申请日：2022-04-14
发明人： Kangguo Cheng , Carl Radens
摘要： The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.
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公开(公告)号：US20230171132A1
公开(公告)日：2023-06-01
申请号：US17898851
申请日：2022-08-30
发明人： Jueon Kim , Taehyoung Kim , Seungjin Park , Jihwan Hyun , Myoungbo Kwak , Junghwan Choi
IPC分类号： H04L25/03 , H03K5/24 , H03K21/08 , H04L27/06 , G01R31/317
CPC分类号： H04L25/03057 , H03K5/24 , H03K21/08 , H04L27/06 , G01R31/31703
摘要： An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.
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公开(公告)号：US11626874B2
公开(公告)日：2023-04-11
申请号：US17502741
申请日：2021-10-15
发明人： Achal Kathuria , Pradeep Jayaraman
摘要： Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
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公开(公告)号：US11476855B2
公开(公告)日：2022-10-18
申请号：US16749223
申请日：2020-01-22
申请人： RAYTHEON COMPANY
发明人： Richard E. Wahl
摘要： An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.
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公开(公告)号：US11442800B2
公开(公告)日：2022-09-13
申请号：US16985362
申请日：2020-08-05
摘要： A windowed watchdog circuit system can include a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold. The windowed watchdog circuit system can include a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorted than the fast threshold. The windowed watchdog circuit system can be configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively.
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公开(公告)号：US20220224340A1
公开(公告)日：2022-07-14
申请号：US17609469
申请日：2021-05-20
发明人： Ruiping LI
IPC分类号： H03K21/08 , H03K17/687
摘要： A counting circuit and a chip are disclosed. The counting circuit includes a charge counter module including a pulse processing module and a first capacitor. The pulse processing module is configured to covert a received pulse signal into a counting current and to transfer the converted counting current to the first capacitor. The first capacitor is configured to receive the counting current and store charge carried in the counting current. The counting circuit takes a voltage of the first capacitor as a basis for counting. The input voltage pulse signal is converted into a current signal in the form of micro pulses for charging the non-variable capacitor, and a counting result is obtained by detecting the voltage of the first capacitor, achieving the following advantages: no need to take care of whether the input pulse signal is continuous or discrete; high resistance to interference; adaptiveness to various input pulse signals of different waveforms and/or with different frequencies; and the ability to solve the problem with the conventional counting circuits that they may not be able to cope with irregular pulse signals and may even not be able to operate normally when such an irregular pulse signal is input.
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