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    SILICON CARBIDE DOPED OXIDE HARDMASK FOR SINGLE AND DUAL DAMASCENE INTEGRATION
    2.
    发明申请
    SILICON CARBIDE DOPED OXIDE HARDMASK FOR SINGLE AND DUAL DAMASCENE INTEGRATION 审中-公开
    单碳双极氧化铝硬质合金单晶和双组分聚合

    公开(公告)号：WO2009039139A1

    公开(公告)日：2009-03-26

    申请号：PCT/US2008/076607

    申请日：2008-09-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MATZ, Laura, M. ,  JIANG, Ping, N. ,  DOSTALIK, William, Wesley

    Inventor： MATZ, Laura, M. ,  JIANG, Ping, N. ,  DOSTALIK, William, Wesley

    IPC: H01L21/768 ,  H01L21/82

    CPC classification number: H01L21/31144 ,  H01L21/3148 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Interconnects of integrated circuits (ICs) (100) utilize low-k dielectrics, copper metal lines, dual damascene processing and amplified photoresist chemistry to build ICs with features smaller than 100 nm. Photolithographic processing of interconnects with these elements are subject to resist poisoning from nitrogen in etch stop and hard mask dielectric layers. Attempts to solve this problem cause lower IC circuit performance or higher fabrication process cost and complexity. This invention comprises a method of fabricating interconnects in an IC using layers of silicon carbide doped oxide (SiCO) in a via etch stop layer, in a trench etch stop layer, as a via etch hard mask and as a trench etch hard mask.

    Abstract translation: 集成电路（IC）（100）的互连使用低k电介质，铜金属线，双镶嵌加工和放大的光致抗蚀剂化学，以构建特征小于100nm的IC。 与这些元件的互连的光刻处理在蚀刻停止和硬掩模介电层中受到氮的中毒。 解决这个问题的尝试导致IC电路性能降低或者制造工艺成本和复杂性更高。 本发明包括一种使用在通孔蚀刻停止层中的碳化硅掺杂氧化物（SiCO）的层，在沟槽蚀刻停止层中作为通孔蚀刻硬掩模和作为沟槽蚀刻硬掩模的IC中的互连的制造方法。

    A TECHNIQUE FOR FORMINIG AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES
    3.
    发明申请
    A TECHNIQUE FOR FORMINIG AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES 审中-公开
    用于形成中间层介电材料的技术在上述结构之间增加可靠性，包括闭合间距线

    公开(公告)号：WO2009005788A2

    公开(公告)日：2009-01-08

    申请号：PCT/US2008008153

    申请日：2008-06-30

    Applicant: ADVANCED MICRO DEVICES INC ,  FEUSTEL FRANK ,  FROHBERG KAI ,  PETERS CARSTEN

    Inventor： FEUSTEL FRANK ,  FROHBERG KAI ,  PETERS CARSTEN

    IPC: H01L21/768

    CPC classification number: H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

    Abstract: By removing excess material of an interlayer dielectric material (207, 307) deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material (360), such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material (207, 307) on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material (207, 307) on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material (207, 307) may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

    Abstract translation: 通过除去通过SACVD沉积的层间电介质材料（207,307）的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可减少该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间绝缘材料（207,307）之前形成诸如二氧化硅的缓冲材料（360），从而在沉积过程中产生增强的均匀性，当沉积层间电介质 材料（207,307）在具有不同高固有应力水平的电介质层上。 因此，可以提高层间绝缘材料（207,307）的可靠性，同时保持由SACVD沉积提供的优点。

    SILICON OXIDE INTERFACE LAYER FORMED DURING SILICON CARBIDE ETCH STOP DEPOSITION
    4.
    发明申请
    SILICON OXIDE INTERFACE LAYER FORMED DURING SILICON CARBIDE ETCH STOP DEPOSITION 审中-公开
    硅碳化硅钝化沉积时形成的氧化硅界面层

    公开(公告)号：WO2008144621A1

    公开(公告)日：2008-11-27

    申请号：PCT/US2008/064071

    申请日：2008-05-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MATZ, Laura, M. ,  TSUI, Ting, Y. ,  BRIGGS, Thad, E. ,  KRAFT, Robert

    Inventor： MATZ, Laura, M. ,  TSUI, Ting, Y. ,  BRIGGS, Thad, E. ,  KRAFT, Robert

    IPC: H01L21/28

    CPC classification number: H01L21/3148 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834

    Abstract: In accordance with the principles of the invention, semiconductor devices (100) and methods of making semiconductor devices and dielectric stack (101) in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure (170) including one or more copper interconnects and forming an etch stop layer (110) over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer (120) over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer (130) over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

    Abstract translation: 根据本发明的原理，提供半导体器件（100）以及在集成电路中制造半导体器件和电介质叠层（101）的方法。 在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构（170），并在第一处理室中在半导体结构上形成蚀刻停止层（110）。 该方法还可以包括在第一处理室中的蚀刻停止层上形成薄氧化硅层（120），并在第二处理室中在薄氧化硅层上形成超低k电介质层（130），其中形成 与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质叠层相比，薄的氧化硅层改善了蚀刻停止层和超低k电介质之间的粘合性。

    METHOD OF IMPROVING THE WAFER TO WAFER UNIFORMITY AND DEFECTIVITY OF A DEPOSITED DIELECTRIC FILM
    8.
    发明申请
    METHOD OF IMPROVING THE WAFER TO WAFER UNIFORMITY AND DEFECTIVITY OF A DEPOSITED DIELECTRIC FILM 审中-公开
    将波形改善到沉积介质膜的均匀性和缺陷度的方法

    公开(公告)号：WO2005103327A1

    公开(公告)日：2005-11-03

    申请号：PCT/US2005/004916

    申请日：2005-02-11

    Applicant: TOKYO ELECTRON LIMITED ,  FUKIAGE, Noriaki

    Inventor： FUKIAGE, Noriaki

    IPC: C23C16/44

    CPC classification number: C23C16/4404 ,  C23C16/4405 ,  H01J37/32862 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/3148

    Abstract: A method and apparatus are included that provide an improved deposition process for a Tunable Etch Resistant ARC (TERA) layer with improved wafer to wafer uniformity and reduced particle contamination. More specifically, the processing chamber is seasoned to reduce the number of contaminant particles generated in the chamber during the deposition of the TERA layer and improve wafer to wafer uniformity. The apparatus includes a chamber having an upper electrode at least one RF source, a substrate holder, and a showerhead for providing multiple precursors and process gasses.

    Abstract translation: 包括一种方法和装置，其提供了具有改进的晶片到晶片均匀性和减少的颗粒污染的可调谐蚀刻ARC（TERA）层的改进的沉积工艺。 更具体地说，处理室被调节以减少在沉积TERA层期间在室中产生的污染物颗粒的数量，并且将晶片提高到晶片的均匀性。 该装置包括具有至少一个RF源的上电极的腔室，衬底保持器和用于提供多个前体和处理气体的喷头。

    ULTRA-THIN FILM FORMATION USING GAS CLUSTER ION BEAM PROCESSING
    9.
    发明申请
    ULTRA-THIN FILM FORMATION USING GAS CLUSTER ION BEAM PROCESSING 审中-公开
    使用气体离子束加工的超薄膜形成

    公开(公告)号：WO2010101688A1

    公开(公告)日：2010-09-10

    申请号：PCT/US2010/023014

    申请日：2010-02-03

    Applicant: TEL EPION INC. ,  HAUTALA, John, J. ,  BURKE, Edmund ,  RUSSELL, Noel ,  HERDT, Gregory

    Inventor： HAUTALA, John, J. ,  BURKE, Edmund ,  RUSSELL, Noel ,  HERDT, Gregory

    IPC: C23C14/22 ,  H01L21/768

    CPC classification number: C23C14/221 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/7684 ,  Y10S438/902

    Abstract: A method of preparing a thin film on a substrate (152, 252, 30') is described. The method comprises forming an ultra-thin hermetic film (40', 71, 622, 762, 812, 832) over a portion of a substrate (152, 252, 30') using a gas cluster ion beam (GCIB) (128), wherein the ultra-thin hermetic film (40', 71, 622, 762, 812, 832) has a thickness less than approximately 5 nm. The method further comprises providing a substrate (152, 252, 30') in a reduced-pressure environment, and generating a GCIB (128) in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are selected to achieve a thickness of the thin film (40', 71, 622, 762, 812, 832) less than about 5 nanometers (nm). The GCIB (128) is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate (152, 252, 30') according to the beam dose. By doing so, the thin film (40', 71, 622, 762, 812, 832) is formed on the at least a portion of the substrate (152, 252, 30') to achieve the thickness desired.

    Abstract translation: 描述了在衬底（152,252,30'）上制备薄膜的方法。 该方法包括使用气体簇离子束（GCIB）（128）在衬底（152,252,30'）的一部分上形成超薄密封膜（40'，71,622,762,812,832） ，其中所述超薄密封膜（40'，71,622,762,812,832）具有小于约5nm的厚度。 该方法还包括在减压环境中提供衬底（152,252,30'），以及在减压环境中从加压气体混合物产生GCIB（128）。 选择光束加速电位和光束剂量以获得小于约5纳米（nm）的薄膜（40'，71,622,762,812,832）的厚度。 GCIB（128）根据光束加速电位被加速，并且加速的GCIB根据光束剂量照射到衬底（152,252,30'）的至少一部分上。 通过这样做，薄膜（40'，71,622,762,812,832）形成在衬底（152,252,30'）的至少一部分上，以实现所需的厚度。

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