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    HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS
    3.
    发明申请
    HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS 审中-公开
    用于减少基板损耗的高电阻率硅绝缘体制造方法

    公开(公告)号：WO2016036318A1

    公开(公告)日：2016-03-10

    申请号：PCT/SG2015/050300

    申请日：2015-09-04

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED

    Inventor： LIU, Qingmin

    IPC: H01L21/762

    CPC classification number: H01L21/76254 ,  H01L21/02112 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/324 ,  H01L27/12 ,  H01L29/0649

    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm: a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

    Abstract translation: 提供了一种多层复合结构体及其制备方法。 多层复合结构包括具有至少约500欧姆 - 厘米的最小体区电阻率的半导体处理衬底：与半导体处理衬底接触的IVA族氮化物层，选自氮化碳 ，碳氮化硅及其组合; 与IVA族氮化物层接触的电介质层; 以及与电介质层接触的半导体器件层。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：WO2015053378A1

    公开(公告)日：2015-04-16

    申请号：PCT/JP2014/077117

    申请日：2014-10-02

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： YAMAZAKI, Shunpei ,  HOSAKA, Yasuharu ,  OBONAI, Toshimitsu ,  KOEZUKA, Junichi ,  SHIMA, Yukinori ,  HAYAKAWA, Masahiko ,  HAMOCHI, Takashi ,  HIRAISHI, Suzunosuke

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L21/477 ,  H01L21/02112 ,  H01L21/02403 ,  H01L21/28 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/7869

    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

    Abstract translation: 为了抑制电特性的改变，并提高使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的栅电极，与栅电极重叠的氧化物半导体膜，位于栅电极和氧化物半导体膜之间并与氧化物半导体膜的表面接触的栅极绝缘膜， 与氧化物半导体膜的表面的相对表面接触的保护膜和与氧化物半导体膜接触的一对电极。 在栅极绝缘膜或保护膜中，通过热处理释放的质荷比为m / z为17的气体的量比通过热处理释放的氮氧化物的量大。

    半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置
    5.
    发明申请
    半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 审中-公开
    用于半导体连接保护的玻璃组合物，用于制造半导体器件的方法和半导体器件

    公开(公告)号：WO2013168623A1

    公开(公告)日：2013-11-14

    申请号：PCT/JP2013/062513

    申请日：2013-04-26

    Applicant: 新電元工業株式会社

    Inventor： 伊東　浩二 ,  小笠原　淳 ,  六鎗　広野

    IPC: H01L21/316 ,  C03C3/091 ,  C03C3/093 ,  C03C8/02

    CPC classification number: H01L23/564 ,  C03C3/091 ,  C03C3/093 ,  C03C8/02 ,  C03C2204/00 ,  C03C2205/00 ,  C03C2207/00 ,  H01L21/02112 ,  H01L21/316 ,  H01L21/76232 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/66136 ,  H01L29/8611 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: 　少なくともＳｉＯ ２ と、Ｂ ２ Ｏ ３ と、Ａｌ ２ Ｏ ３ と、アルカリ土類金属の酸化物とを含有し、かつ、Ｐｂと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋと、Ｚｎとを実質的に含有しない原料を溶融させて得られる融液から作製されたガラス微粒子からなり、かつ、フィラーを含まないことを特徴とする半導体接合保護用ガラス組成物。　本発明の半導体接合保護用ガラス組成物によれば、鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス材料」を用いた場合と同様に、高耐圧の半導体装置を製造することが可能となる。また、Ｚｎを実質的に含有しないことから、耐薬品性（特に耐フッ酸性）が高くなり、高信頼性の半導体装置を製造することが可能となる。また、シリコン酸化膜をエッチング除去する工程などでガラス層をレジストで保護する必要がなくなるため、工程を簡略化できるという効果も得られる。

    Abstract translation: 一种用于半导体结保护的玻璃组合物，包括由熔融物形成的玻璃微粒，所述熔体通过熔化至少含有SiO 2，B 2 O 3，Al 2 O 3和碱土金属的氧化物的原料，并且基本上不含Pb，As， Sb，Li，Na，K和Zn，玻璃组合物的特征在于不含填料。 通过使用通过该半导体结保护用玻璃组合物使用不含铅的玻璃材料，可以制造半导体器件，上述具有高耐压性的半导体器件类似于常规的“含硅酸铅的玻璃材料 主要成分“。 此外，由于上述玻璃组合物基本上不含有Zn，因此能够制造高可靠性的半导体装置，耐化学性（特别是耐氢氟酸性）得到改善。 此外，可以简化步骤，因为在通过蚀刻去除氧化硅膜的步骤期间不再需要用抗蚀剂保护玻璃层。

    FABRICATION OF INTEGRATED CIRCUITS UTILIZING THICK HIGH-RESOLUTION PATTERNS
    7.
    发明申请
    FABRICATION OF INTEGRATED CIRCUITS UTILIZING THICK HIGH-RESOLUTION PATTERNS 审中-公开
    使用高分辨率图案集成电路的制造

    公开(公告)号：WO1980000639A1

    公开(公告)日：1980-04-03

    申请号：PCT/US1979000702

    申请日：1979-09-07

    Applicant: WESTERN ELECTRIC CO INC

    Inventor： WESTERN ELECTRIC CO INC ,  FRASER D ,  MAYDAN D ,  MORAN J

    IPC: H01L21/312

    CPC classification number: H01L21/0338 ,  G03F7/094 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/0278 ,  H01L21/312

    Abstract: In an integrated circuit fabrication sequence, a relatively thick sacrificial layer (18) is deposited on a nonplanar surface of a device wafer in which high-resolution features are to be defined. The thick layer is characterized by a conforming lower surface and an essentially planar top surface and by the capability of being patterned in a high-resolution way. An intermediate masking layer (22) and then a thin resist layer (20) are deposited on the top surface of the sacrificial layer, the thickness of the resist layer being insufficient by itself to provide adequate step coverage if the resist layer were applied directly on the nonplanar surface. A high-resolution pattern defined in the resist layer is transferred into the intermediate masking layer. Subsequently, a dry processing technique is utilized to replicate the pattern in the sacrificial layer. A high-resolution pattern with near-vertical sidewalls is thereby produced in the sacrificial layer. By means of the patterned sacrificial layer, high-resolution features are then defined in the underlying nonplanar surface.

    METHODS OF FABRICATING FEATURES ASSOCIATED WITH SEMICONDUCTOR SUBSTRATES
    8.
    发明申请
    METHODS OF FABRICATING FEATURES ASSOCIATED WITH SEMICONDUCTOR SUBSTRATES 审中-公开
    制造与半导体基板相关的特征的方法

    公开(公告)号：WO2016160156A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/018175

    申请日：2016-02-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： SILLS, Scott E. ,  SANDHU, Gurtej S.

    IPC: H01L21/027

    CPC classification number: H01L21/702 ,  H01L21/02112 ,  H01L21/02359 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086

    Abstract: Some embodiments include a method in which a mixture of polynucleotide structures comprises a set of surface shapes. Surface shapes of some polynucleotide structures are complementary to surface shapes of other polynucleotide structures. The complementary surface shapes lock together along interfaces between adjacent polynucleotide structures to incorporate the polynucleotide structures into a polynucleotide mask. The polynucleotide mask is used during fabrication of features associated with a semiconductor substrate. Some embodiments include a method in which a semiconductor substrate comprises registration regions configured to adhere individual polynucleotide structures to specific locations of the semiconductor substrate. The adhered polynucleotide structures are incorporated into a polynucleotide mask which is used during fabrication of features associated with the semiconductor substrate.

    Abstract translation: 一些实施方案包括多核苷酸结构的混合物包含一组表面形状的方法。 一些多核苷酸结构的表面形状与其他多核苷酸结构的表面形状互补。 互补表面形状沿相邻多核苷酸结构之间的界面锁定在一起，以将多核苷酸结构并入多核苷酸掩模。 在制造与半导体衬底相关的特征时使用多核苷酸掩模。 一些实施例包括其中半导体衬底包括被配置成将单个多晶核苷酸结构粘附到半导体衬底的特定位置的配准区域的方法。 将粘附的多核苷酸结构并入到在与半导体衬底相关联的特征的制造期间使用的多核苷酸掩模中。

    METHOD OF MANUFACTURING A GERMANIUM-ON-INSULATOR SUBSTRATE
    10.
    发明申请
    METHOD OF MANUFACTURING A GERMANIUM-ON-INSULATOR SUBSTRATE 审中-公开
    绝缘体绝缘子基板的制造方法

    公开(公告)号：WO2015178857A1

    公开(公告)日：2015-11-26

    申请号：PCT/SG2015/050121

    申请日：2015-05-22

    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  NANYANG TECHNOLOGICAL UNIVERSITY

    Inventor： LEE, Kwang Hong ,  TAN, Chuan Seng ,  TAN, Yew Heng ,  CHONG, Gang Yih ,  FITZGERALD, Eugene A. ,  BAO, Shuyu

    IPC: H01L21/02 ,  H01L27/12

    CPC classification number: H01L21/76256 ,  H01L21/02057 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3247

    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.

    Abstract translation: 公开了一种制造绝缘体上锗衬底的方法。 该方法包括：提供（102）第一半导体衬底和形成有锗层的第二半导体衬底; 使用至少一种介电材料将所述第一半导体衬底接合（102）到所述第二半导体衬底以形成组合衬底，所述锗层布置在所述第一和第二半导体衬底之间; 从所述组合的衬底去除（104）所述第二半导体衬底以暴露所述锗层的至少一部分具有失配位错; 以及退火（106）所述组合的衬底以使得能够从所述锗层的所述部分去除所述失配位错。

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