公开(公告)号：WO2013028435A1

公开(公告)日：2013-02-28

申请号：PCT/US2012/050953

申请日：2012-08-15

Applicant: Marvell World Trade Ltd. ,  KAO, Huahung ,  LIOU, Shiann-Ming

Inventor： KAO, Huahung ,  LIOU, Shiann-Ming

IPC: H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Abstract translation: 本公开的实施例提供了一种包装装置，包括底部包装和第二包装。 第一包装包括基底层，其包括（i）顶侧和（ii）与顶侧相对的底侧。 此外，顶侧限定基本平坦的表面。 第一封装还包括耦合到衬底层的底侧的管芯。 第二封装包括多排焊球，并且第二封装通过多排焊球附接到基板层的基本上平坦的表面。

公开(公告)号：WO2014018538A1

公开(公告)日：2014-01-30

申请号：PCT/US2013/051694

申请日：2013-07-23

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Sehat

IPC: H01L23/00

CPC classification number: H01L23/36 ,  H01L21/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.

Abstract translation: 在一个实施例中，提供了一种包括衬底的包装装置; 耦合到所述衬底的多存储器管芯，其中所述多存储器管芯包括多个单独存储器管芯，并且所述多个独立存储器管芯中的每一个在存储器管芯的制造期间被定义为半导体材料的晶片内的单个存储器管芯，以及 多存储器管芯是通过将半导体材料的晶片分成存储器管芯而形成的，其中至少一个存储器管芯是包括仍然物理连接在一起的多个独立存储器管芯的多存储器管芯; 以及耦合到所述多存储器管芯和所述衬底的半导体管芯，其中所述半导体管芯被配置为芯片上的系统，其中所述多存储器管芯和所述半导体管芯中的至少一个附接到所述衬底。