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    INTERFACIAL LAYER REGROWTH CONTROL IN HIGH-K GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR
    1.
    发明申请
    INTERFACIAL LAYER REGROWTH CONTROL IN HIGH-K GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR 审中-公开
    场效应晶体管的高K栅结构的界面层响应控制

    公开(公告)号：WO2009156954A1

    公开(公告)日：2009-12-30

    申请号：PCT/IB2009/052709

    申请日：2009-06-24

    Applicant: NXP B.V. ,  MUELLER, Markus ,  BOCCARDI, Guillaume ,  PETRY, Jasmine

    Inventor： MUELLER, Markus ,  BOCCARDI, Guillaume ,  PETRY, Jasmine

    IPC: H01L21/28 ,  H01L29/51 ,  H01L21/3115

    CPC classification number: H01L29/51 ,  H01L21/265 ,  H01L21/28176 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/4236 ,  H01L29/49 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78 ,  H01L29/78696

    Abstract: A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO 2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO 2 layer adjacent a channel region of the field effect transistor;a high-K dielectric layer on the SiO 2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO 2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO 2 interfacial layer inhibits regrowth of the SiO 2 layer into the channel region during the annealing step.

    Abstract translation: 具有栅极结构的场效应晶体管包括高K电介质层，位于高K电介质层上的栅电极以及位于高K电介质层与场效应晶体管的沟道区之间的界面层 。 界面层包含含有再生长抑制剂的SiO 2层。 一种形成栅极结构的方法包括：形成栅叠层，其顺序包括：与场效应晶体管的沟道区相邻的SiO 2层; SiO 2层上的高K电介质层; 以及在高K电介质层上的栅电极。 该方法还包括将再生长抑制剂引入SiO 2层中，然后对栅极结构进行退火。 在SiO 2界面层中再生抑制剂的存在在退火步骤期间抑制SiO 2层进入沟道区的再生长。

    METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR
    3.
    发明申请
    METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR 审中-公开
    制造双极晶体管的方法

    公开(公告)号：WO2008026175A1

    公开(公告)日：2008-03-06

    申请号：PCT/IB2007/053476

    申请日：2007-08-29

    Applicant: NXP B.V. ,  DONKERS, Johannes, J., T., M. ,  NUTTINCK, Sebastien ,  BOCCARDI, Guillaume L., R. ,  NEUILLY, Francois

    Inventor： DONKERS, Johannes, J., T., M. ,  NUTTINCK, Sebastien ,  BOCCARDI, Guillaume L., R. ,  NEUILLY, Francois

    IPC: H01L21/331 ,  H01L29/737 ,  H01L29/40

    CPC classification number: H01L29/7378 ,  H01L29/407 ,  H01L29/66242

    Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.

    Abstract translation: 本发明提供了制造双极晶体管的替代和较不复杂的方法，其包括在与集电极区域（21）相邻的沟槽（7）中的场板（17），该场板（17）采用减小的表面场（Resurf ）效果。 Resurf效应重塑了集电极区域（21）中的电场分布，使得对于相同的集电极 - 基极击穿电压，可以有效地增加集电极区域（21）的掺杂浓度，从而降低集电极电阻，从而增加双极性 晶体管速度。 该方法包括在第一基层（4）中形成基窗（6）从而暴露集电区（21）的顶表面和隔离区（3）的一部分的步骤。 通过去除隔离区域（3）的露出部分形成沟槽（7），之后隔离层（9,10）形成在沟槽（7）的表面上。 在隔离层（10）上形成第二基层（13），从而在集电区域（21）的顶面上形成场板（17），从而形成基极区域（31） 从而在第一基底层（4），基底区域（31）和场板（17）之间形成电连接。 在基极区域（31）的顶部形成发射极区域（41），从而形成Resurf双极型晶体管。

    GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR
    5.
    发明申请
    GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR 审中-公开
    场效应晶体管的门结构

    公开(公告)号：WO2009133515A1

    公开(公告)日：2009-11-05

    申请号：PCT/IB2009/051714

    申请日：2009-04-27

    Applicant: NXP B.V. ,  MUELLER, Markus ,  BOCCARDI, Guillaume ,  PETRY, Jasmine

    Inventor： MUELLER, Markus ,  BOCCARDI, Guillaume ,  PETRY, Jasmine

    IPC: H01L21/28 ,  H01L21/265 ,  H01L29/51 ,  H01L21/3115

    CPC classification number: H01L21/26506 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/31155 ,  H01L21/32155 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises Al x Si y O z , which has a higher relative dielectric constant value than SiO 2 . A method of forming the gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO 2 -based layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO 2 -based layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing Al into the SiO 2 -based layer to form an Al x Si y O z interfacial layer in between the high-K dielectric layer and the channel region. A heating step to allows Al introduced into channel region to diffuse out of the channel region into the interfacial layer.

    Abstract translation: 具有栅极结构的场效应晶体管包括位于晶体管沟道区域和栅极叠层的高K电介质层之间的界面层。 界面层包含Al x Se y O z，其比SiO 2具有更高的相对介电常数值。 一种形成场效应晶体管的栅极结构的方法。 该方法包括形成栅极堆叠，其顺序包括：与场效应晶体管的沟道区相邻的基于SiO 2的层; 在SiO 2基层上的高K电介质层; 以及在高K电介质层上的栅电极。 该方法还包括将Al引入SiO 2基层中以在高K电介质层和沟道区之间形成Al x Se y O z界面层。 加热步骤，允许引入通道区域的Al扩散到沟​​道区域内进入界面层。

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