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    THERMAL VIAS DISPOSED IN A SUBSTRATE PROXIMATE TO A WELL THEREOF
    4.
    发明申请
    THERMAL VIAS DISPOSED IN A SUBSTRATE PROXIMATE TO A WELL THEREOF 审中-公开
    在基材中处理的热叶可以很好地替代

    公开(公告)号：WO2015134993A1

    公开(公告)日：2015-09-11

    申请号：PCT/US2015/019517

    申请日：2015-03-09

    Applicant: INVENSAS CORPORATION

    Inventor： KATKAR, Rajesh ,  SITARAM, Arkalgud, R. ,  UZOH, Cyprian, Emeka

    IPC: H01L23/367

    CPC classification number: H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

    Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

    Abstract translation: 装置一般涉及三维堆叠集成电路。 在这种装置中，三维堆叠集成电路具有至少第一管芯和第二管芯，使用管芯到管芯互连彼此互连。 第一管芯的衬底具有至少一个热通孔结构，其从衬底的下表面朝向衬底的阱延伸，而不延伸到阱并且不延伸通过衬底。 所述至少一个热通孔结构的第一端至少足够靠近所述衬底的阱，用于将热量传导出来。 衬底具有从衬底的下表面延伸到衬底的上表面的至少一个穿过衬底通孔结构。 所述至少一个热通孔结构的第二端与所述第二管芯的至少一个通孔通孔结构耦合以进行导热。

    CAPACITIVE COUPLING OF INTEGRATED CIRCUIT DIE COMPONENTS
    5.
    发明申请
    CAPACITIVE COUPLING OF INTEGRATED CIRCUIT DIE COMPONENTS 审中-公开
    集成电路组件的电容耦合

    公开(公告)号：WO2017058422A1

    公开(公告)日：2017-04-06

    申请号：PCT/US2016/048889

    申请日：2016-08-26

    Applicant: INVENSAS CORPORATION

    Inventor： SITARAM, Arkalgud, R. ,  HABA, Belgacem

    IPC: H01L23/522 ,  H01L23/50

    CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/31111 ,  H01L23/642 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/27452 ,  H01L2224/27614 ,  H01L2224/29187 ,  H01L2224/32135 ,  H01L2224/83896 ,  H01L2225/06531 ,  H01L2924/01072 ,  H01L2924/0534 ,  H01L2924/05442 ,  H01L2924/30105

    Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

    Abstract translation: 提供集成电路管芯部件和其他导电区域的电容耦合。 要耦合的每个部件具有包括至少一个导电区域的表面，例如金属焊盘或板。 在至少一个待耦合的表面上形成一层超薄电介质。 当两个部件（例如，每个管芯中的一个）永久地接触在一起时，电介质的超薄层保留在两个表面之间，在每个相应部件的导电区域之间形成电容器或电容接口。 电介质的超薄层可以由多层各种电介质组成，但是在一个实施方案中，总厚度小于约50纳米。 形成的电容接口的每单位面积的电容取决于在超薄层中使用的电介质材料的特定介电常数κ及其各自的厚度。 电气和接地连接可以在耦合堆叠的边缘进行。

    WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY
    9.
    发明申请
    WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY 审中-公开
    电路结构中的波纹减少

    公开(公告)号：WO2015084848A2

    公开(公告)日：2015-06-11

    申请号：PCT/US2014/068162

    申请日：2014-12-02

    Applicant: INVENSAS CORPORATION

    Inventor： WOYCHIK, Charles, G. ,  UZOH, Cyprian, Emeka ,  CAO, Andrew ,  SITARAM, Arkalgud, R.

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L21/32051 ,  H01L21/78 ,  H01L22/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

    Abstract translation: 为了减少晶片的至少一个区域中的翘曲，形成应力/翘曲管理层（810）以使现有翘曲的方向超平衡并改变。 例如，如果该地区的中部相对于该地区的边界膨胀，该区域的中部可能会向下膨胀，反之亦然。 然后处理压力/翘曲管理层以减少过度平衡。 例如，应力/管理层可以在选定位置从晶片剥离，或者可以在层中形成凹陷，或者可以在该层中引起相变。 在其它实施例中，该层是钽 - 铝，其可能或可能不会使翘曲过度平衡; 这一层被认为是由于结晶相依赖的应力而减少翘曲，其动态地适应温度变化，以便减少翘曲（可能通过热循环保持晶片平坦）。 还提供其他功能。

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