公开(公告)号：WO2017011228A1

公开(公告)日：2017-01-19

申请号：PCT/US2016/041000

申请日：2016-07-05

Applicant: INVENSAS CORPORATION

Inventor： UZOH, Cyprian, Emeka

IPC: H01L23/00 ,  H01L23/12 ,  H01L21/324 ,  H01L23/485

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13355 ,  H01L2224/13409 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13813 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/8184 ,  H01L2224/83815 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/013

Abstract: A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.

Abstract translation: 制造组件的方法可以包括在第一部件的基板的第一表面处形成第一导电元件，通过暴露于化学镀浴，在导电元件的表面上形成导电纳米颗粒，并置第一导电的表面 元件，其具有在第二部件的基板的主表面处的第二导电元件的对应表面，并且至少在并置的第一和第二导电元件的界面处将温度升高到导电纳米颗粒引起冶金接头的接合温度 在并置的第一和第二导电元件之间形成。 导电纳米颗粒可以设置在第一和第二导电元件的表面之间。 导电纳米颗粒可以具有小于100纳米的长尺寸。

公开(公告)号：WO2016123609A3

公开(公告)日：2016-09-29

申请号：PCT/US2016015951

申请日：2016-02-01

Applicant: INVENSAS CORP

Inventor： KATKAR RAJESH ,  UZOH CYPRIAN EMEKA ,  SITARAM ARKALGUD R

IPC: H01L23/485 ,  H01L21/60 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L21/768 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81007 ,  H01L2224/81048 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01327 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

Abstract translation: 装置一般涉及微电子器件。 在这样的装置中，第一基板具有第一表面，第一表面具有位于第一表面上的第一互连，并且第二基板具有第二表面，第二表面与第一表面隔开，第一表面与第二表面之间具有间隙。 第二个互连位于第二个表面上。 第一互连的下表面和第二互连的上表面为了第一基板和第二基板之间的导电性而彼此耦合。 导电套环围绕第一和第二互连的侧壁，介电层围绕导电套环。

公开(公告)号：WO2016123609A2

公开(公告)日：2016-08-04

申请号：PCT/US2016/015951

申请日：2016-02-01

Applicant: INVENSAS CORPORATION

Inventor： KATKAR, Rajesh ,  UZOH, Cyprian, Emeka ,  SITARAM, Arkalgud, R.

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L24/81 ,  H01L21/768 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81007 ,  H01L2224/81048 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01327 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

Abstract translation: 一种装置一般涉及一种微电子装置。 在这种装置中，第一基板具有第一表面，第一互连位于第一表面上，第二基板具有与第一表面间隔开的第二表面，第一表面与第二表面之间具有间隙。 第二互连位于第二表面上。 第一互连件的下表面和第二互连件的上表面彼此耦合，用于在第一基板和第二基板之间的导电性。 导电套环在第一和第二互连的侧壁周围，并且电介质层围绕导电套环。

公开(公告)号：WO2010062254A1

公开(公告)日：2010-06-03

申请号：PCT/SG2008/000448

申请日：2008-11-27

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  NANYANG TECHNOLOGICAL UNIVERSITY ,  WEI, Jun ,  ANG, Xiao Fang ,  WONG, Chee Cheong ,  CHEN, Zhong

Inventor： WEI, Jun ,  ANG, Xiao Fang ,  WONG, Chee Cheong ,  CHEN, Zhong

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/2007 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13793 ,  H01L2224/13824 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/13886 ,  H01L2224/1389 ,  H01L2224/13893 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3512 ,  H01L2924/36 ,  Y10T428/25 ,  Y10T428/254 ,  Y10T428/31678 ,  H01L2924/01074 ,  H01L2924/00

Abstract: A method for forming direct metal-metal bond between metallic surfaces is disclosed. The method comprises depositing a first nanostructured organic coating (118) on a first metallic surface (116) to form a first passivation layer thereon, the first nanostructured organic coating (118) comprising an organic phase with nanoparticles dispersed within the organic phase, contacting the first nanostructured organic coating (118) with a second metallic surface (126), and applying on the first and second metallic surfaces (116, 126) at least a bonding temperature of at least room temperature and/or a bonding pressure for a bonding period to bond the first and second metallic surfaces (116, 126) thereby forming the direct metal-metal bond therebetween. A second nanostructured organic coating (128) comprising an organic phase with nanoparticles dispersed within the organic phase may also be deposited on the second metallic surface (126).

Abstract translation: 公开了在金属表面之间形成直接金属 - 金属结合的方法。 该方法包括在第一金属表面（116）上沉积第一纳米结构化有机涂层（118）以在其上形成第一钝化层，第一纳米结构有机涂层（118）包含有机相，纳米颗粒分散在有机相内， 具有第二金属表面（126）的第一纳米结构有机涂层（118），并且在第一和第二金属表面（116,126）上至少施加至少室温的粘结温度和/或粘合时间段的粘合压力 以接合第一和第二金属表面（116,126），从而在它们之间形成直接金属 - 金属粘合。 包含分散在有机相内的纳米颗粒的有机相的第二纳米结构有机涂层（128）也可沉积在第二金属表面（126）上。