公开(公告)号：WO2011054554A1

公开(公告)日：2011-05-12

申请号：PCT/EP2010/061902

申请日：2010-08-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  HOUGHAM, Gareth, Geoffrey ,  MCVICKER, Gerard ,  GU, Xiaoxiong

发明人： HOUGHAM, Gareth, Geoffrey ,  MCVICKER, Gerard ,  GU, Xiaoxiong

IPC分类号： H01L21/48 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/81101 ,  H01L2224/81208 ,  H01L2224/81899 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/15333 ,  H01R13/02 ,  H01R13/2421 ,  H01R43/16 ,  H05K3/064 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/10265 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49208 ,  Y10T29/49218 ,  Y10T29/49222 ,  Y10T29/49224 ,  H01L2924/00

摘要： A structure and method for manufacturing the same for manufacturing a contact structure for microelectronics manufacturing including the steps of forming first and second metal sheets to form a plurality of outwardly extending bump each defining a cavity. Symmetrically mating the first and second metal sheets in opposing relation to each other to form upper and lower bumps each defining an enclosure therebetween wherein the mated first and second sheets form a contact structure. Coating the contact structure with an insulating material, and fabricating helix shaped contacts from upper and lower bumps. The helix shaped contacts having first and second portions being in mirror image relationship to each other.

摘要翻译： 一种用于制造用于微电子制造的接触结构的结构和方法，包括以下步骤：形成第一和第二金属片以形成多个向外延伸的凸起，每个限定腔。 将第一和第二金属板彼此相对地对称地配合，以形成每个限定其间的外壳的上凸块和下凸块，其中配合的第一和第二板形成接触结构。 用绝缘材料涂覆接触结构，并从上部和下部凸块制造螺旋形接触。 具有彼此成镜像关系的第一和第二部分的螺旋形接触件。

公开(公告)号：WO2006105015A2

公开(公告)日：2006-10-05

申请号：PCT/US2006/011094

申请日：2006-03-24

申请人： STATS CHIPPAC LTD. ,  PENDSE, Rajendra, D.

发明人： PENDSE, Rajendra, D.

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

摘要翻译： 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹。

公开(公告)号：WO2005048311A2

公开(公告)日：2005-05-26

申请号：PCT/US2004/037647

申请日：2004-11-10

申请人： CHIPPAC, INC. ,  PENDSE, Rajendra, D.

发明人： PENDSE, Rajendra, D.

IPC分类号： H01L

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.

摘要翻译： 通过将互连凸块直接配合到引线上而不是在捕获垫上来制造倒装芯片互连。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中具有导电迹线的衬底，其中凸块直接配合到迹线上。 在一些实施例中，互连是在不使用焊接掩模的情况下形成的。 在一些方法中，可固化粘合剂分配到模具上的凸块上或衬底上的迹线上; 粘合剂在配合过程中部分固化，并且部分固化的粘合剂用于在回流过程中限制熔融焊料。

公开(公告)号：WO2002080271A2

公开(公告)日：2002-10-10

申请号：PCT/US2002/005087

申请日：2002-02-21

申请人： INTEL CORPORATION

发明人： KUBOTA, Jiro ,  TAKAHASHI, Kenji

IPC分类号： H01L23/485

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/1607 ,  H01L2224/75252 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H05K3/24 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/0195 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00

摘要： A flip chip method of joining a chip and a substrate is described. A thermocompression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow temperature of the solder bumps is reach ed. Proximate with reaching the re-flow temperature at the solder bumps, th contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

摘要翻译： 描述了一种连接芯片和基板的倒装芯片方法。 使用热压接机来对准芯片和衬底，并施加接触力以将衬底上的焊料凸块保持在芯片上的金属凸块上。 芯片通过焊接机头部的脉冲加热器从其非本机侧快速加热，直到焊料凸块的再流动温度达到最高。 近似达到焊料凸点处的回流温度时，释放接触力。 焊料被保持在其再流动温度以上几秒钟以便于衬底的金属突起和接合的润湿。 由贵金属如钯构成的金属盖被施加到金属凸块的表面，以防止金属凸块（其通常包括高导电性和高反应性金属如铜）在刚好在高温下的高温下氧化 并在重新流动操作期间。

公开(公告)号：WO2017083015A1

公开(公告)日：2017-05-18

申请号：PCT/US2016/053083

申请日：2016-09-22

申请人： INTEL CORPORATION

发明人： SAHASRABUDHE, Shubhada H. ,  SANE, Sandeep B. ,  KUMAR, Siddarth ,  TANDON, Shalabh

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/488

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

摘要： Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

摘要翻译： 这里通常讨论的是用于通过模具互连（TMI）更可靠地封装（PoP）封装的方法和设备。 器件可以包括第一管芯封装和第二管芯封装，第一管芯封装包括在第一管芯封装上或者至少部分地在第一管芯封装中的第一导电焊盘，在第一管芯封装上的电介质模制材料，模制材料包括穿过其中的至少部分地暴露焊盘的孔， 包括在第二管芯上或至少部分地在第二管芯中的第二导电焊盘的管芯封装将第二管芯封装封装在模具材料上，使得第二导电焊盘通过孔面对第一导电焊盘，并且在孔中形成形状记忆结构， 第一管芯封装和第二管芯封装之间的焊料柱电连接的一部分。

公开(公告)号：WO2010062254A1

公开(公告)日：2010-06-03

申请号：PCT/SG2008/000448

申请日：2008-11-27

申请人： AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  NANYANG TECHNOLOGICAL UNIVERSITY ,  WEI, Jun ,  ANG, Xiao Fang ,  WONG, Chee Cheong ,  CHEN, Zhong

发明人： WEI, Jun ,  ANG, Xiao Fang ,  WONG, Chee Cheong ,  CHEN, Zhong

IPC分类号： H01L21/3205 ,  H01L21/28

CPC分类号： H01L21/2007 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13793 ,  H01L2224/13824 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/13886 ,  H01L2224/1389 ,  H01L2224/13893 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3512 ,  H01L2924/36 ,  Y10T428/25 ,  Y10T428/254 ,  Y10T428/31678 ,  H01L2924/01074 ,  H01L2924/00

摘要： A method for forming direct metal-metal bond between metallic surfaces is disclosed. The method comprises depositing a first nanostructured organic coating (118) on a first metallic surface (116) to form a first passivation layer thereon, the first nanostructured organic coating (118) comprising an organic phase with nanoparticles dispersed within the organic phase, contacting the first nanostructured organic coating (118) with a second metallic surface (126), and applying on the first and second metallic surfaces (116, 126) at least a bonding temperature of at least room temperature and/or a bonding pressure for a bonding period to bond the first and second metallic surfaces (116, 126) thereby forming the direct metal-metal bond therebetween. A second nanostructured organic coating (128) comprising an organic phase with nanoparticles dispersed within the organic phase may also be deposited on the second metallic surface (126).

摘要翻译： 公开了在金属表面之间形成直接金属 - 金属结合的方法。 该方法包括在第一金属表面（116）上沉积第一纳米结构化有机涂层（118）以在其上形成第一钝化层，第一纳米结构有机涂层（118）包含有机相，纳米颗粒分散在有机相内， 具有第二金属表面（126）的第一纳米结构有机涂层（118），并且在第一和第二金属表面（116,126）上至少施加至少室温的粘结温度和/或粘合时间段的粘合压力 以接合第一和第二金属表面（116,126），从而在它们之间形成直接金属 - 金属粘合。 包含分散在有机相内的纳米颗粒的有机相的第二纳米结构有机涂层（128）也可沉积在第二金属表面（126）上。

公开(公告)号：WO2005048311A3

公开(公告)日：2006-01-05

申请号：PCT/US2004037647

申请日：2004-11-10

申请人： CHIPPAC INC ,  PENDSE RAJENDRA D

发明人： PENDSE RAJENDRA D

IPC分类号： G01R31/26 ,  H01L20060101 ,  H01L21/56 ,  H01L21/60 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： A flip chip interconnect is made by mating the interconnect bump (104) directly onto a lead (114), rather than onto a capture pad. Also, a flip chip package includes a die (102) having solder bumps (104) attached to interconnect pads in an active surface, and a substrate (112) having electrically conductive traces (114) in a die attach surface (113), in which the bumps (104) are mated directly onto the traces (114). In some embodiments the interconnection is formed without employing a solder mask (86). In some methods a curable adhesive (122) is dispensed either onto the bumps (104) on the die (102) or onto the traces (114) on the substrate (112); the adhesive (122) is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.

摘要翻译： 通过将互连凸块（104）直接配置到引线（114）而不是到捕获垫上而制成倒装芯片互连。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块（104）的裸片（102）和在芯片附接表面（113）中具有导电迹线（114）的衬底（112） 其中凸块（104）直接配合到迹线（114）上。 在一些实施例中，互连是在不使用焊接掩模（86）的情况下形成的。 在一些方法中，将可固化粘合剂（122）分配到模具（102）上的凸块（104）上或衬底（112）上的迹线（114）上。 粘合剂（122）在配合过程中部分固化，并且部分固化的粘合剂用于在回流过程中限制熔融焊料。

公开(公告)号：WO2009146007A3

公开(公告)日：2010-01-21

申请号：PCT/US2009038708

申请日：2009-03-29

申请人： INTEL CORP ,  MAHAJAN RAVI ,  SANE SANDEEP

发明人： MAHAJAN RAVI ,  SANE SANDEEP

IPC分类号： H01L23/48

CPC分类号： H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

摘要： A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

摘要翻译： 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：WO2009146007A2

公开(公告)日：2009-12-03

申请号：PCT/US2009/038708

申请日：2009-03-29

申请人： INTEL CORPORATION ,  MAHAJAN, Ravi ,  SANE, Sandeep

发明人： MAHAJAN, Ravi ,  SANE, Sandeep

IPC分类号： H01L23/48

CPC分类号： H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

摘要： A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

摘要翻译： 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：WO2006105015A3

公开(公告)日：2007-11-22

申请号：PCT/US2006011094

申请日：2006-03-24

申请人： STATS CHIPPAC LTD ,  PENDSE RAJENDRA D

发明人： PENDSE RAJENDRA D

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

摘要： A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

摘要翻译： 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹。