摘要:
An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another; an insulator layer directly contacting the top surface; and a via coupling a contact bump to the top metal layer portion; wherein a first vertical axis, orthogonal to a substrate coupled to the backend portion, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion. Other embodiments are described herein.
摘要:
A microelectronic assembly (10, 110, 210, 310, 410) includes a first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) having a first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a second substrate (14, 114, 214, 314, 414) having a second conductive element (26, 126, 226, 326, 426). The assembly further includes an electrically conductive alloy mass (16, 116) joined to the first and second conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022), including a first, a second and a third material. First and second materials of the alloy mass (16, 116) each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) to a relatively lower amount toward the second conductive element (26, 126, 226, 326, 426), and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element (26, 126, 226, 326, 426) to a relatively lower amount toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022). The microelectronic assembly (10, 110, 210, 310, 410) is formed by aligning the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912), having a first bond component (30, 230, 330, 430), with the second substrate (14, 114, 214, 314, 414), having a second bond component (40, 240, 340, 440), such that the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components are in contact with each other, the first bond component (30, 230, 330, 430, 1030) including a first material layer (36, 536, 636, 736, 836, 936) adjacent the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a first protective layer (38, 538, 638, 738, 838, 938) overlying the first material layer (36, 536, 636, 736, 836, 936), the second bond component (40, 240, 340, 440) including a second material layer (46) adjacent the second conductive element (26) and a second protective layer (48) overlying the second material layer (46), and heating the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components such that at least portions of the first (36, 536, 636, 736, 836, 936) and second (46) material layers diffuse together to form the alloy mass (16, 116) joining the first (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and second (14, 114, 214, 314, 414) substrates with one another. There may be formed a plurality of first conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) on the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and a plurality of second conductive elements (26, 126, 226, 326, 426) on the second substrate (14, 114, 214, 314, 414), joined by a plurality of conductive alloy masses (16, 116). The conductive alloy mass (116) may also surround and hermetically seal an internal volume.
摘要:
Un composant de connexion électro-mécanique (10) muni sur une face de connexion d'inserts conducteurs (72) est destinés à être insérés dans des plots conducteurs respectifs (18) ménagés sur une face d'un autre composant de connexion (12) pour une hybridation du type face contre face. Chaque insert (72) du composant (10) comprend : une âme métallique creuse (50) constituée d'un fond disposé sur la face de connexion (14) et d'une paroi latérale faisant saillie dudit fond, définissant une surface interne de l'insert (72), au moins une portion de ladite surface interne étant non oxydée; et une couche métallique (70) recouvrant sensiblement uniquement la surface interne de l'âme métallique (50). Selon un mode de réa lisation, la couche métallique (70) comprende une première sous- couche (80) d'un métal oxydable et une seconde sous-couche (82) d'oxyd natif du métal consitutif de la première sous-couche (80).
摘要:
L'invention concerne un procédé d'assemblage de deux composants électroniques l'un à l'autre, lesdits composants comportant chacun une face d'assemblage, selon lequel on rapproche les deux faces d'assemblage l'une de l'autre selon une direction X dite d'assemblage et on applique une force donnée F à l'un et/ou l'autre des composants, l'une et/ou l'autre face(s) d'assemblage comportant: -des inserts de connexion en matériau rigide présentant une forme longitudinale allongée selon la direction X d'assemblage; -des pistes de connexion en matériau de dureté inférieure à celle des inserts et de forme longitudinale allongée transversalement à la direction X d'assemblage. procédé selon lequel: -on aligne les inserts en regard des pistes correspondantes de manière à ce que les inserts et les pistes forment deux à deux, après assemblage, au moins une intersection sensiblement transversale, -on applique la force F pour faire pénétrer les inserts dans les pistes jusqu'à obtenir l'assemblage.
摘要:
A component 10 can include a substrate 20 and a conductive via 40 extending within an opening 30. The substrate 20 can have first and second opposing surfaces 21, 22. A dielectric material 60 can be exposed at an inner wall 32 of the opening 30. The conductive via 40 can define a relief channel 55 within the opening 30 adjacent the first surface 21. The relief channel 55 can have an edge 56 within a first distance D1 from the inner wall 32 in a direction D2 of a plane P parallel to and within five microns below the first surface 21, the first distance being the lesser of one micron and five percent of a maximum width of the opening 30 in the plane. The edge 56 can extend along the inner wall 32 to span at least five percent of a circumference of the inner wall.
摘要:
Un procédé de réalisation d'un dispositif hybridé consiste : à réaliser un premier composant (10) muni de billes métalliques (14), et un second composant (12) muni d'éléments de connexion (40, 42); fixer les billes (14) avec les éléments de connexion (40, 42). La fabrication du second composant (12) comporte : la réalisation, sur une face d'un substrat, d'éléments résistifs (24) aux emplacements prévus pour les éléments de connexion (40, 42); le dépôt d'une couche d'un isolant électrique (34) sur les éléments résistifs (24); et la réalisation des éléments de connexion (40, 42) comportant chacun un puits métallique (40) présentant une ouverture apte à recevoir la bille métallique (14) correspondante du premier composant microélectronique (10) et au moins partiellement rempli d'un élément fusible, notamment de l'indium ou un alliage d'étain et d'or, ou d'une encre conductrice (42), notamment à base d'argent ou de cuivre. La fabrication du puits métallique (40) comporte la réalisation d'une plage métallique (36) déposées sur la couche constituée d'un poly¬ mère fluoré et la découpe au laser d'une ouverture dans ladite plage métallique (36). En outre, la fixation des billes (14) avec les éléments de connexion (40, 42) comporte l'application d'un courant électrique au travers des éléments résistifs (24) de manière à échauffer les billes (14).
摘要:
In sophisticated semiconductor devices (200) including copper-based metallization systems, a substantially aluminum-free bump structure (212D) in device regions (250D) and a substantially aluminum-free wire bond structure (212T) in test regions (250T) may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks (203) in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices (202D). For example, nickel contact elements may be formed above copper-based contact areas (207D, 207T) wherein the nickel (213) may provide a base for wire bonding or forming a bump material thereon.
摘要:
An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.