US10432442B2
A method for transmitting multiple communications of different types, in particular sporadic (MTC) or cellular (broadband) communication including symbols to be transmitted, corresponding to communication services implementing a modulation having M subcarriers of the FBMC-OQAM or OFDM-OQAM type. The method uses linear frequency filtering of a sequence of length N including symbols having L coefficients that are parametrizable according to the communication, L, N, and M being natural numbers, so as to generate N+L−1 symbols, reducing out-of-band spurious emissions. The method also uses, no matter what the communication is, a single frequency/time transform (IFFT) having a size M, where N
US10432440B2
A method is proposed for generating an OFDM type multicarrier signal including OFDM blocks constituted by M carriers modulated by source symbols. The method includes the following steps: interleaving the M symbols of a block of source symbols into R sub-blocks of N interleaved symbols; obtaining a block of M time domain samples corresponding to the block of M source symbols; forming a peak vector containing N maximum amplitudes determined from among the M samples; attenuating the extrema of each sub-block of N time domain samples corresponding to the R sub-blocks of N interleaved symbols by a correction of symbols taking account of the peak vector and delivering R sub-blocks of N corrected interleaved symbols; de-interleaving the R sub-blocks of N corrected interleaved symbols delivering a block of M corrected source symbols; generating an OFDM block of the signals corresponding to the block of M corrected source symbols.
US10432436B1
A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.
US10432432B1
An electronic circuit, including an equalizer circuit to input a differential signal, a rectifier circuit to receive the differential signal and output a first current and a second current, a replica circuit to receive a differential threshold signal and output a third current and a fourth current to compensate for PVT variations in the first and second currents, and a comparator circuit configured to compare a differential voltage generated based on the first, second, third, and fourth currents to determine a loss of signal event of the electronic circuit.
US10432430B2
Aspects of the present invention relate to methods, systems, and computer-readable media for triggering an identification signal broadcast of a first navigational aid equipment using a tone in the voice band transmitted by a second navigational aid equipment. Aspects include receiving, at the first navigational aid equipment, a tone in a voice band of second navigational aid equipment. Aspects also include transmitting, by the first navigational aid equipment, the identification associated with the first navigational aid equipment identification when the tone is received.
US10432429B1
A token bucket or leaky bucket is maintained at least partially through the use of two separate counters. A full counter, is maintained in relatively lower cost memory, and indicates the amount of tokens within the bucket on a potentially delayed basis. An intermediate counter is stored in a relatively higher cost memory that supports high access rates, and indicates the amount of tokens assigned (or unassigned) to the bucket since the full counter was last updated. Various adjustment processes remove (or add) tokens as needed for performing tasks. A background process updates the full counter from the corresponding intermediate counter on a periodic, scheduled, or other basis. The buckets are replenished (or deleted) with tokens periodically at assigned rates. Traffic management or other decisions are based on the bucket's current status, as determined from the full counter during the background process and then stored in the higher cost memory.
US10432427B2
A first network element comprising a memory comprising instructions executable by a processor and a processor coupled to the memory and configured to execute the instructions. Executing the instructions causes the processor to receive, from a second network element during a border gateway protocol communication session, a communications capabilities message indicating capabilities of the second network element, receive, from the second network element, an advertisement message indicating connections and accesses of a second domain controlled by the second network element, receive a request to route data between a source located in a first domain and a destination, transmit a first request message to the second network element to cause the second network element to compute a path segment through the second domain, and transmit a second request message to create a segment of an end-to-end tunnel between the source and the destination crossing the first domain and the second domain.
US10432421B2
Provided are a communication control device and a communication system capable of detecting message transmission in the case where an invalid device transmits a message to a common communication line. A monitoring device decides a reference time point t0 for periodical message transmission by an ECU, decides multiple scheduled transmission time points t1, t2, . . . obtained by adding a period corresponding to an integer multiple of a transmission cycle T of a message to the reference time point t0, and decides that a predetermined period including each of the scheduled transmission time points is a permission period for message transmission. The monitoring device determines whether or not a detected message on a CAN bus has been transmitted during the permission period. If determined that transmission of an invalid message is not permitted, the monitoring device performs processing of causing the ECU which receives the message to discard the message.
US10432418B1
Methods and systems may provide for technology to extract relationship data from one or more social networks and generate a trust network based on the relationship data, wherein the trust network identifies one or more trusted individuals. The technology also grants access to the smart device system with respect to the one or more trusted individuals.
US10432415B2
A method for interference aware communications of devices in a wireless local area network is provided. The device selects a transmission channel of a frame among a plurality of sub-channels, generates interference aware information based on an interference condition of the plurality of sub-channels, inserts the interference aware information into the frame, and transmits the frame in the selected transmission channel.
US10432403B2
An infusion pump and server computer have improved network access security. The infusion pump has a network interface circuit to provide communications over a network and a processing circuit that generates infusion pump data for transmission to a remote server computer. The processing circuit generates a header portion of a request message having at least one field, hashes the header portion but not payload data using a cryptographic hash function and a cryptographic key to provide a hashed code, and inserts the hashed code into the header portion of the request message. The processing circuit inserts the infusion pump data into a body portion of the request message and transmits the request message to the remote server computer over the communications network.
US10432398B1
A regression on a prime-indexed-prime finite difference generator function is used to predict prime numbers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US10432395B2
A system that includes a quantum key device, a first device, and a second device. A monitor module is configured to detect, at the first device, that the second device is reading quantum information over a second quantum communication channel. A read module is configured to read, at the first device, the quantum information over a first quantum communication channel. An encryption module is configured to generate a first quantum encryption key at the first device using the quantum information that is read over the first quantum communication channel. The encryption module is also configured to encrypt data using the first quantum encryption key to create encrypted data. The second device decrypts the encrypted data using a second quantum encryption key generated at the second device using the quantum information read at the second device to create decrypted data.
US10432389B2
A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
US10432380B2
A device may determine one or more parameters relating to a network. The device may detect a trigger to alter a hybrid automatic repeat request (HARQ) configuration for the network based on the one or more parameters relating to the network. The device may determine an alteration to the HARQ configuration based on detecting the trigger to alter the HARQ configuration. The device may communicate with a distributed unit or a centralized unit of the network to cause the alteration to the HARQ configuration.
US10432379B2
Methods and apparatus to enable an extensible and scalable control channel for wireless networks. In one embodiment, an Enhanced Physical Downlink Control Channel (ePDCCH) is disclosed that is implemented with a flexible number of Physical Resource Blocks (PRBs). Advantages of the ePDCCH include, for example: more efficient spectral utilization, better frequency management across multiple serving entities (e.g., base stations and remote radio heads), and extensible payload capabilities that can scale to accommodate higher or lower control information payloads, as compared to prior art PDCCH solutions.
US10432376B2
In mixed numerology case, the performance of a physical downlink shared channel (PDSCH) can be improved by multiplexing PDSCH of one numerology with the channel state information reference signals (CSI-RS) of the other numerology and use of an advanced receiver. However, due to the interference from the PDSCH of the other numerology, the channel estimation for the underlying UE can be impacted if the CSI-RS is corrupted. An adaptive CSI-RS configuration can be deployed where the CSI-RS density is adapted based on the PDSCH transmission of the other numerology. Namely, based on the scheduling decision of the other numerology, the CSI-RS density can be changed. Thus, the impact on channel estimation can be minimized when the data channel of one numerology is multiplexed with the CSI-RS of the other numerology.
US10432371B2
Embodiments of the present invention disclose a data transmission method, user equipment, and a base station. The method include: receiving a first reference signal set; obtaining, based on the first reference signal set and a first codeword-to-layer mapping, CSI that includes a rank indicator RI and a channel quality indicator CQI, and sending the CSI; receiving a second reference signal set; and receiving, based on the second reference signal set and a second codeword-to-layer mapping, data, where a quantity of layers to which at least one codeword is mapped in the first codeword-to-layer mapping is less than a quantity of layers to which a codeword is mapped in the second codeword-to-layer mapping. According to the embodiments of the present invention, precision of an MCS used during data transmission may be improved, and a throughput of a communications system may be enhanced.
US10432370B2
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be a UE. The UE identifies properties associated with reference signals of a received payload. The properties associated with reference signals of the received payload may include a reference signal structure and/or a traffic to pilot ratio. The UE determines a payload structure based on the identified properties. Subsequently, the UE decodes the received payload based on the determined payload structure. The UE may receive mapping information indicating a mapping between possible properties associated with reference signals and possible payload structures. The UE may determine the payload structure further based on the received mapping information. The UE may receive the mapping information through a broadcast or RRC signaling.
US10432369B2
A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and processing circuitry, among other possible circuitries, components, elements, etc. to support communications with other WDEV(s) and to generate and process signals for such communications. The WDEV supports first communications with another WDEV to determine an agreed-upon orthogonal frequency division multiple access (OFDMA) resource unit (RU) and agreed-upon OFDMA sub-carriers to be used by the other WDEV to provide predetermined response(s). The WDEV then transmits a question to the WDEV and processes the plurality of agreed-upon OFDMA sub-carriers within the OFDMA RU to determine whether energy therein indicates a response of the one or more predetermined responses to the question being received from the other WDEV in accordance with second communications.
US10432366B2
In some embodiments, a wireless device such as a user equipment (UE) may communicate with a base station using an advanced form of carrier aggregation. The UE may provide signaling to the network specifying a number P of downlink component carriers to be configured for use by the UE for downlink carrier aggregation and a number Q of uplink component carriers to be configured for use by the UE for uplink carrier aggregation. The UE can only utilize a lesser number M of downlink component carriers at any given time in downlink carrier aggregation and can only utilize a lesser number N of uplink component carriers at any given time in uplink carrier aggregation. Thus the UE may request the network to configure a greater number P and Q of downlink and uplink component carriers, respectively, than the UE can actually use at any instant of time.
US10432362B2
Hybrid automatic repeat request (HARQ) processes, indicators, and similar methods may be used improve new radio performance in a number of ways. For example HARQ processes may be retransmitted, even before a response is expected, a number of times. Separate acknowledgement may be provided for various code blocks within a single transport block. Multi-bit ACK/NACK signaling may be used to efficiently express the status of individual code blocks or groups of code blocks within a transmission block. Grantless transmissions may be acknowledged implicitly, e.g., via responses comprising downlink control information or sent via a physical hybrid automatic repeat request indicator channel.
US10432357B2
Methods, systems, and devices that support an efficient sequence-based polar code description are described. In some cases, a wireless device (e.g., a user equipment (UE) or a base station) may transmit a codeword including a set of information bits encoded using a polar code or receive a codeword including a set of information bits encoded using a polar code. As described herein, the wireless device may determine the bit locations of the information bits in the polar code based on a partition assignment vector. Specifically, the wireless device may partition bit-channels for one or more stages of polarization and assign information bits to partitions based on the partition assignment vector. Once the bit locations of the information bits are determined, the wireless device may decode a received codeword or transmit an encoded codeword based on the determined bit locations of the information bits.
US10432348B2
A wireless signal transmission method includes: transmitting, by a transmitting station, a wireless signal to a plurality of receiving stations, wherein the wireless signal comprises a first portion and a second portion, the first portion being a trigger frame with a first type of frame format which can be independently decoded, the second portion being a specific signal with a second type of frame format; and receiving, by the transmitting station, a radio frame transmitted by at least one of the plurality of receiving stations. The wireless signal transmission method provided by the present disclosure are used to solve the problems in the prior art that a trigger frame is not able to complete transmission resources reservation and trigger multi-user transmission at the same time as satisfying the training accuracy required for uplink multi-user transmission.
US10432341B2
A transmitter for transmitting an optical signal in an optical communication system includes a plurality of light sources configured to output optical signals; a plurality of first optical couplers configured to multiplex the optical signals, which are output from the plurality of light sources, to generate a first optical signal, and output the first optical signal through a first output port and a second output port of each of the plurality of first optical couplers; a first monitoring unit configured to monitor the first optical signal which is output through the second output port of each of the plurality of first optical couplers; and a controller configured to control an optical output of each of the plurality of light sources on the basis of a result of the monitoring.
US10432328B2
An automatic system level testing (ASLT) system for testing smart devices is disclosed. The system comprises a system controller operable to be coupled with a smart device in an enclosure, wherein the system controller comprises a memory comprising test logic and a processor. The system also comprises the enclosure, wherein the enclosure comprises a plurality of components, the plurality of components comprising: (i) a robotic arm comprising a stylus, wherein the stylus is operable to manipulate the smart device to simulate human interaction therewith; and (ii) a platform comprising a device holder, wherein the device holder is operable to receive a smart device inserted there into. The processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic.
US10432326B2
The present disclosure discloses a method, an apparatus, a device, and a system for antenna alignment. The method includes: performing, according to a target preset condition, adjustment processing on a phase and an amplitude of a signal that is transmitted by each antenna unit of a first antenna, and the second antenna is located within a coverage scope of the target beam; and determining that a difference between a horizontal angle of the target beam and a mechanical horizontal angle of a current mechanical location of the first antenna is a horizontal angle, that needs to be adjusted, of the first antenna, adjusting the mechanical horizontal angle and the mechanical pitch angle of the first antenna according to the horizontal angle that needs to be adjusted and the pitch angle that needs to be adjusted.
US10432324B2
A method for performing self-interference removal by a communication device using a full-duplex radio (FDR) mode, according to an embodiment of the present invention, comprises a step for branching a residual self-interference signal, after removal of an antenna self-interference signal, into a plurality of reception RF chains. And the present invention enables determining of whether or not digital self-interference removal is to be performed after combining the plurality of self-interference signals, which have been branched, on the basis of a predefined threshold and strength of each of the plurality of self-interference signals that have been branched.
US10432322B2
The present disclosure relates to a transmission/reception device, a transmission/reception method, and a program capable of improving a transmission characteristic in human body communication in both transmission and reception. The transmission/reception device used for human body communication includes three electrodes including a human body side electrode being in contact with a human body as a communication medium, a space side electrode provided on a space side, not a human body side, and a circuit board provided with a circuit. At this time, at the time of transmission, a switch between the space side electrode and the circuit board is turned off to make a three-pole electrode configuration having superiority in the transmission characteristic, and each electrode is caused to function as an independent electrode. On the other hand, at the time of reception, the switch between the space side electrode and the circuit board is turned on to electrically short-circuit the space side electrode and the circuit board, to cause the electrodes to function as a two-pole electrode configuration having superiority in the transmission characteristic. The present disclosure can be applied to a human body communication device.
US10432310B2
Systems and methods for optical modulation index calibration in a CATV network.
US10432304B2
Various examples are provided for jamming avoidance response (JAR), and photonic implementations thereof. In one example, a method includes generating optical pulses that correspond to raising envelope of a beat signal associated with an interference signal and a reference signal; generating optical spikes that correspond to positive zero crossing points of the reference signal; and providing a phase output that indicates whether the beat signal is leading or lagging the reference signal, the phase output based at least in part upon the optical spikes. An adjustment to a reference frequency can be determined based at least in part upon the optical pulses and the phase output. In another example, a JAR system includes photonic circuitry to generate the optical pulses; photonic circuitry to generate the optical spikes; and photonic circuitry to provide the phase output. A logic unit can determine the adjustment to the reference frequency.
US10432287B2
Disclosed are a method for transmitting/receiving channel state information in a wireless communication system and a device for same. In particular, a method of reporting channel state information (CSI), by a user equipment (UE) in a wireless communication system comprises the steps of: receiving, from an eNB, a CSI process configuration comprising interference measurement restriction information indicating interference measurement restriction; and reporting, to the eNB, CSI corresponding to a CSI process configured by the CSI process configuration, wherein when a first subframe set and a second subframe set are configured for the CSI process, the interference measurement restriction can be independently configured for each of the first subframe set and the second subframe set.
US10432286B2
The present invention relates to a method for receiving a reference CSI configuration information and a following CSI configuration information which is configured to report a same RI (Rank Indicator) as the reference CSI configuration information, receiving a first precoding codebook subset information for the reference CSI configuration information and a second precoding codebook subset information for the following CSI configuration information, set of RIs according to the second precoding codebook subset information is same as set of RIs according to the first precoding codebook subset information, and transmitting CSI determined based on at least one of the first precoding codebook subset information and the second preceding codebook subset information.
US10432285B2
A method includes: generating, by user equipment, at least one piece of channel state information, wherein each piece of channel state information in the at least one piece of channel state information is corresponding to at least one resource unit required for sending data by a base station; and sending, by the user equipment, multiple pieces of channel state information, so that the base station sends data on a corresponding resource unit according to channel state information. Therefore, channel state information sent by the user equipment is associated with a resource unit required for sending data by the user equipment.
US10432280B1
Systems and methods are provided for improving uplink coverage in a wireless communication network. A first correlated array and a second correlate array each comprise a plurality of antenna elements. Each correlated array has an inter-element spacing of one wavelength of a signal for which the array is configured to receive. The first and second correlated arrays are interleaved such that one-half of a wavelength of a signal for which at least one of the correlated arrays is configured to receive separates adjacent elements of the first and second correlated arrays. Signals received by each correlated array are combined using statistical signal processing techniques to create combined signals that may be provided to the wireless communication network. Combining uplink signals from at least two interleaved uncorrelated arrays may increase the effective spacing of each array without sacrificing base station space or throughput.
US10432273B1
There is provided an antenna arrangement. The antenna arrangement comprises a first antenna array and a second antenna array. Each antenna array comprises antenna elements of a first polarization and antenna elements of a second polarization. The two antenna arrays are arranged to collectively be fed four signals, such that the antenna elements of each polarization at each antenna array is fed a respective one out of the four signals. The signal as fed to the antenna elements of the second polarization of the second antenna array is phase shifted 180° with respect to at least one of the other signals as fed to the other antenna elements.
US10432270B2
A multiplexed space-time block coding (M-STBC) scheme is described that allows for transmitting a single multicast transmission in a heterogeneous MIMO (i.e., multiple-input and multiple-output) environment, where receivers with fewer antennas can receive a lower resolution version of the multi-cast transmission, while receivers with a greater number of antennas can receive a higher resolution version of the multi-cast transmission. Thus, the M-STBC scheme allows for transmitting the single multicast transmission that includes both a spatial multiplexing mode and a diversity mode.
US10432263B2
Systems and methods which utilize wireless charging to initiate near field communication (NFC) pairing between mobile systems which utilize wireless charging and wireless charging base stations. Wireless signals sent by a mobile system over a wireless charging channel are used to initiate communication between an NFC reader presented in a base station and a passive NFC tag (or an active NFC tag used in a passive mode) present in the mobile system. Such feature allows the mobile system to act as an initiator for NFC communication without requiring the mobile system to be equipped with an NFC reader. A wireless power receiver of a mobile system may communicate with a wireless power transmitter of a base station using backscatter modulation. Commands of a standard wireless charging protocol may be repurposed to send a request for initiation of an NFC session from a mobile system to a base station.
US10432257B2
Methods, systems, and apparatus for monitoring and controlling electronic devices using wired and wireless protocols are disclosed. The systems and apparatus may monitor their environment for signals from electronic devices. The systems and apparatus may take and disambiguate the signals that are received from the devices in their environment to identify the devices and associate control signals with the devices. The systems and apparatus may use communication means to send control signals to the identified electronic devices. Multiple apparatuses or systems may be connected together into networks, including mesh networks, to make for a more robust architecture.
US10432256B2
A system that reduces crosstalk and return loss within electrical communication connectors includes at least two compensating capacitors connected in series that compensate each offending capacitor. An additional inductive component that is connected between two compensating capacitors so that the adjustable inductance of the inductive component can be varied to modify the capacitive coupling effect achieved by the compensating capacitors as a function of frequency. A shape-neutral structure containing two compensating capacitors and one series inductive component in between is positioned so that each compensating capacitor is juxtaposed parallel to the offending capacitor. There is no direct contact between the shape-neutral structure and the transmission lines, and the shape-neutral structure does not change the shape of PCB traces and reduces both crosstalk and return loss.
US10432252B2
Binary forward error correcting (FEC) encoding is applied to a stream of input bits, to generate a stream of coded bits. The coded bits are mapped to multiple binary streams. In some embodiments, at least one coded bit is mapped to more than one of the binary streams and none of the binary streams are identical to each other. Stream-specific modulations are applied to the binary streams. Non-binary FEC encoding could be applied after the stream-specific modulations.
US10432251B2
A receiver includes a reception antenna, a reception unit, and a demodulation unit. The reception unit sequentially receives modulated signals resulting from spread spectrum via the reception antenna. The demodulation unit demodulate a first signal received by the reception unit by performing despreading using a short-period spreading code, the first signal including information for identifying a long-period spreading code. The demodulation unit identifies the long-period spreading code on the basis of the information obtained from the first signal. The demodulation unit then demodulates a second signal received by the reception unit after the first signal by performing despreading using the long-period spreading code.
US10432244B2
A system with one or more transceiver antenna assemblies for installation in vehicle side-view mirrors to enable communication with nearby vehicles. Each transceiver antenna assembly may have one or two antenna arrays implemented on a single printed circuit board, protected by an antenna housing used to mount the transceiver antenna inside the mirror assembly. Each antenna array in a dual-channel transceiver antenna may transmit and receive data over one of two DSRC channels. One channel may be used to transmit and receive vehicle data only and the other channel may be used to transmit and receive both vehicle data and audio/video (A/V) data. Each antenna array is connected to a radio in the vehicle that processes received signals and prepares signals for transmission. Such a transceiver antenna system may be especially useful for communication in truck platooning.
US10432239B2
The invention relates to a lighting device, comprising a first lighting means and a transmission module for wireless transmission and for providing a position identification signal comprising position determination data. The lighting device also comprises an electronic operating device for operating the first lighting means, wherein the electronic operating device is coupled on the input side to an electrical supply connection of the lighting device and on the output side to the first lighting means by a first connection device. The electronic operating device comprises an energy converter for supplying the transmission module with electrical energy. The invention further relates to a system for providing a position indication having a plurality of such lighting devices. In addition, the invention relates to a method for operating a lighting device having a first lighting means by providing a position identification signal comprising position determination data by means of a transmission module.
US10432238B1
Detuning and isolation techniques for a multiband tunable matching network used in multi-transceiver RF systems. Embodiments include an amplifier and a multiband tunable matching network (MN) coupled to the amplifier. The multiband tunable MN is configured to detune to an isolation OFF state from an ON state, wherein the match tuning in the isolation OFF state is different than match tuning in the ON state. In an example detuning, the match tuning in the isolation OFF state is in a different frequency band than a frequency band of match tuning in the ON state and is selected based on the frequency band of match tuning in the ON state.
US10432235B2
A multiplexing system can include a first diplexer and a second diplexer. The first diplexer can be configured to filter a first transmit signal received at the first transmit terminal to a first cellular frequency band and output the filtered first transmit signal at the first common terminal. The first diplexer can be further configured to filter a first receive signal to a second cellular frequency band and output the filtered first receive signal at the first receive terminal input. The second diplexer can be configured to filter a second transmit signal received at the second transmit terminal to the second cellular frequency band and output the filtered second transmit signal at the second common terminal. The second diplexer can be further configured to filter a second receive signal to the first cellular frequency band and output the filtered second receive signal at the second receive terminal.
US10432227B2
Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
US10432220B2
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
US10432210B1
Continuous-time pipeline analog-to-digital converters can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the continuous-time circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the continuous-time circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.
US10432198B1
Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.
US10432190B2
A semiconductor device comprises a first transistor with a silicon carbide layer between the source and the drain electrodes and between the gate and drain electrodes. A diode is formed in the silicon carbide layer. A forward voltage of the diode varies with the voltage applied to the gate electrode of the first transistor. A second transistor is connected to the first transistor. A gate controller applies voltages to gates of the first and second transistor such that the first and second transistors are set to an off-state a first time. The first gate voltage is then increased to an intermediate voltage that is less than a threshold voltage of the first transistor. The intermediate voltage is sufficient to alter the forward voltage of the diode and permit a forward current to flow in the diode. The first gate voltage is then increased to an on-state voltage.
US10432188B2
A ringing suppression circuit connected to a transmission line to suppress ringing caused by the transmission line transmitting a differential signal using a pair of signal lines, the differential signal varying between a high level and a low level, the pair of signal lines including a high potential signal line and a low potential signal line, the ringing suppression circuit including: an inter-line switching element that is connected between the pair of signal lines; a control portion that performs a ringing suppression operation in response to detecting a level change in the differential signal, wherein the ringing suppression operation turns on the inter-line switching element to decrease an impedance between the pair of signal lines; and a suppression operation prohibiting portion that prohibits the control portion from performing the ringing suppression operation in response to detecting a signal caused by a signal on the transmission line.
US10432181B2
A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.
US10432179B1
We disclose frequency doublers for use in millimeter-wave devices. One such frequency doubler comprises at least one passive mixer comprising at least one of the following: at least one transistor configured to receive a back gate voltage; at least one first input driver circuit; and two second input driver circuits. We also disclose a method comprising determining a target output voltage of a frequency doubler comprising at least one passive mixer comprising at least one transistor configured to receive a back gate voltage; determining an output voltage of the frequency doubler; increasing a back gate voltage of the at least one transistor, in response to determining that the output voltage is below the target output voltage; and decreasing the back gate voltage of the at least one transistor, in response to determining that the output voltage is above the target output voltage.
US10432176B2
Relaxation oscillator and method for providing an output frequency. For example, the relaxation oscillator includes a reference generator, a capacitor, a first comparator, a second comparator, a latch, and a temperature compensation circuit. The reference generator is configured to generate a first bias current, a first bias voltage and a second bias voltage. The capacitor is configured to be charged by a charging current to generate a charged voltage, and the charging current is generated based on at least the first bias current. The first comparator is configured to compare the charged voltage and the first bias voltage to generate a first comparison result, and the second comparator is configured to compare the charged voltage and the second bias voltage to generate a second comparison result. The latch is configured to generate a clock signal based on at least the first comparison result and the second comparison result.
US10432175B2
Apparatus, devices, and systems to provide a low quiescent current load switch are disclosed. A disclosed load switch circuit includes a transconductor to convert a voltage to a current input to a transistor gate, the current input to the transistor gate to control the gate to deliver power to a load from a power supply. The example circuit includes a resistor to provide power from a charge pump to the gate as controlled by the transconductor. A disclosed apparatus includes a driver to control a gate of a transistor, the gate to enable the transistor to deliver power to a load from a power supply when the gate is activated, and a gate slope control to control a rate of change over time of a voltage associated with the gate to activate the gate and to disable the driver when the gate is activated.
US10432167B2
Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.
US10432165B2
Provided is a balanced/unbalanced converter (1) that includes a first strip line (40), a second strip line (41), a third strip line (42), a fourth strip line (43), an unbalanced terminal (4), and an open terminal (7). The first strip line (40) includes a spiral first conductor (19), and the second strip line (41) includes a spiral second conductor (14). An outer circumferential end (19b) of the first conductor (19) is electrically connected to the unbalanced terminal (4), and an outer circumferential end (14a) of the second conductor (14) is electrically connected to the open terminal (7).
US10432163B2
The present disclosure provides a variable filter circuit capable of controlling a band width and a center frequency of a pass band, and also capable of suppressing the total number of pieces of variable reactance. That is, a variable filter circuit includes a serial arm in which a plurality of circuit elements are connected in series with respect to a signal path and a parallel arm in which a plurality of circuit elements are connected in parallel with respect to the signal path, wherein the serial arm and the parallel arm each includes a variable reactance element, a series reactance element that is connected in series to the variable reactance element and resonates therewith, and a parallel reactance element that is connected in parallel to the variable reactance element and resonates therewith.
US10432150B2
An apparatus may include a digital-to-analog converter configured to convert a digital audio input signal into a differential analog input signal with a substantially non-zero common-mode voltage, an amplifier configured to receive the differential analog input signal and generate at an amplifier output a ground-centered output signal from the differential analog input signal, a clamp configured to selectively couple and decouple the amplifier output to a ground voltage, and a controller configured to control the clamp to selectively couple and decouple the amplifier output to a ground voltage responsive to transitions between power states of a device comprising the apparatus and control the differential analog input signal generated by the digital-to-analog converter in order to minimize a level transition current through an output load coupled to the amplifier output during transitions between the power states.
US10432148B2
Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
US10432143B2
Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some embodiments, an adjustment block may be employed to adjust the count determined by the learning block based on one or more measured characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.
US10432135B2
The invention relates to a solar roof plate system for laying on an inclined surface, preferably on a roof comprising a roof ridge and an eave, with at least two roof plates comprising an upper side and a lower side, and with a solar module, which extends over the upper side of the roof plates and can be fastened thereto. A profile rail is provided interconnecting the roof plates, which comprises at least one module receptacle for receiving an edge of the solar module, preferably an edge of the solar module facing the eaves or the roof ridge.
US10432131B2
There are provided the same number of inverter modules as the number of phases of a motor, and an inverter control unit that generates PWM signals used to drive the inverter modules in PWM. Three phase outputs from each of the inverter modules are coupled to form a phase output signal for one phase of the motor while capacitors are mounted between control GNDs of the inverter modules and power GNDs of the inverter modules. Consequently, even if a surge voltage is generated in a GND wiring at the time of a switching operation of switching elements in the inverter modules, the application of the surge voltage to the switching elements can be suppressed.
US10432128B2
A frequency converter is used for generating at least one frequency converter output voltage a prescribable frequency converter output voltage amplitude and a prescribable frequency converter output voltage frequency for an electric motor. The frequency converter has: a clocked DC/DC converter is designed to generate from an input direct voltage having an input voltage level a DC/DC converter output voltage having a DC/DC converter output voltage level, wherein the DC/DC converter is designed to generate the DC/DC converter output voltage level based on the prescribable frequency converter output voltage amplitude, and a clocked inverter having a number of controllable switches, to which inverter the DC/DC converter output voltage is applied and which actuates the switches with an inverter switching frequency such that the at least one frequency converter output voltage with the prescribable frequency converter output voltage frequency is generated from the DC/DC converter output voltage.
US10432127B1
A cargo handling system is disclosed. In various embodiments, the cargo handling system includes a direct current power bus; a motor connected to the direct current power bus and having a flux reference input; a unit controller connected to the motor and configured to detect a level of regenerative energy on the direct current power bus and to alter the flux reference input in response to the level of regenerative energy.
US10432111B2
Provided is a self-repairing energy generating element using a shape memory polymer, including a first electrode; a shape memory friction layer made of the shape memory polymer on the first electrode and having a microbump pattern formed on a surface thereof; a second electrode disposed apart from the shape memory friction layer; and an opposing layer formed on the second electrode and configured to face the shape memory friction layer.
US10432105B2
The present disclosure provides a power frequency current converter, including: an input side and an output side, wherein a current of the input side or the output side is a power frequency current; a switching device; and a controller, configured to control the switching device to be turned on and turned off at an operating frequency, wherein within a half of a power frequency cycle, the controller generates at least two fixed-frequency control signals and the operating frequency of the switching device alters at least twice according to the at least two fixed-frequency control signals, so as to reduce junction temperature of the switching device.
US10432104B2
A synchronous switching converter with an energy storage component and a synchronous rectifier coupled to the energy storage component, having: a secondary control circuit configured to receive a slew rate threshold adjusting signal and a voltage across the synchronous rectifier, and to provide a secondary control signal; wherein the secondary control circuit detects a slew rate of the voltage across the synchronous rectifier, and maintains the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold.
US10432099B2
A resonant converter circuit comprising a controller having a Vbusdiv-input-terminal configured to receive a Vbusdiv-input-signal; and a Vbus-compensation-network. The Vbus-compensation-network comprising: a Vbus-input-terminal configured to receive a bus-voltage-signal; and a Vbusdiv-output-terminal configured to provide the Vbusdiv-input-signal to the controller; a reference terminal; an AC-impedance-network connected between the Vbus-input-terminal and the Vbusdiv-output-terminal, wherein the AC-impedance-network is configured to apply an AC transfer function to the received bus voltage signal; a DC-impedance-network connected between the Vbus-input-terminal and the Vbusdiv-output-terminal, wherein the DC-impedance-network is configured to apply a DC transfer function to the received bus voltage signal. The DC transfer function is different to the AC transfer function. The controller is configured to control operation of a resonant converter in accordance with the Vbusdiv-input-signal.
US10432092B2
A controller is configured to perform self-calibration to maintain approximately a desired switching frequency of a power converter. The self-calibration performed by the controller at least partially mitigates detrimental effects associated with variation in an actual switching frequency of the power converter from a designed switching frequency. The controller maintains approximately the desired switching frequency, in one example, in view of a delay inherent in the control by the controller of the power converter.
US10432088B1
A two-stage power converter is disclosed in which a second stage may command a first stage to adjust an output voltage from the first stage to compensate for PVT variations in the second stage. Alternatively, the second stage may adjust a clocking frequency to compensate for the PVT variations.
US10432082B1
An electrical power input adapter coupled to a direct current (DC) bus in a power distribution system receives either an alternating current (AC) power signal or a DC power signal at a first voltage level to transmit to the DC bus. An electrical converter receives and converts the received signal to a DC power signal at a second fixed voltage. A second interface includes a current limiter to receive and limit an amperage of the DC power signal at the second voltage. A programmable switch coupled to the current limiter receives the DC power signal at the second voltage and at the limited amperage and transmits the DC power signal at the second voltage and at the limited amperage. A controller coupled to the programmable switch controls when, within a period of time, the programmable switch is to transmit the DC power signal at the second voltage and at the limited amperage. An integrator receives the DC power signal at the second voltage and at the limited amperage when transmitted within the period of time and converts it to a DC power signal at the second voltage and at a second amperage that is proportional to the limited amperage integrated over the period of time.
US10432080B2
A driving device of a semiconductor device includes a plurality of protection factor detection units, an identification signal generation unit, a continuation signal generation unit, a signal selection unit, and an alarm signal output unit. The protection factor detection units detect an occurrence of a protection factor. The protection factor requires a protection operation of a semiconductor device. The protection factor detection units output a protection factor generation signal. When any protection factor detection units output the protection factor generation signal, the identification signal generation unit generates a protection factor identification signal. The continuation signal generation unit generates a protection factor continuation signal while the protection factor detection unit outputs the protection factor generation signal. The signal selection unit selects the protection factor identification signal and the protection factor continuation signal. The alarm signal output unit outputs a selection signal selected by the signal selection unit as an alarm signal.
US10432076B2
A hybrid electric machine includes N phases (N≥1), each phase having first and second assemblies movable relative to one another and each having a set of teeth made up of a number of teeth that are equally distributed according to a plurality of periods, in which: a. the first assembly is made up of two magnetized parts, each including a magnet magnetically coupled with two toothed yokes, the magnet of one of the magnetized parts being polarized along the same axis but in the opposite direction to the polarization of the magnet of the second magnetized part; b. the second assembly including at least two toothed zones with pitches identical to the pitch of the toothed yokes; c. one of the assemblies has at least two sets of teeth in phase, and the other assembly has at least two sets of teeth which are out of phase by a half-period.
US10432073B2
A medical pump includes a single phase synchronous motor, a rod piston, a cylinder for receiving the rod piston for reciprocating motion therein. The single phase synchronous motor includes a stator and a rotor rotatable relative to the stator. The rotor includes a plurality of permanent magnets. The stator comprises a stator core and a winding wound around the stator core. The stator core comprises two opposed pole portions that define there between a rotor receiving space for receiving the permanent magnets. The medical pump has a compact structure. In addition, the motor of the medical pump has a constant rotation speed and has a smaller size and less weight under the same output power conditions as traditional motors used in medical pumps. The medical pump is particularly suitable for use in atomizers.
US10432054B2
Provided is a vehicle brushless AC generator capable of improving workability and improving insulation property to enhance reliability while preventing a decrease in slot space factor of a stator coil. In the vehicle brushless AC generator, grooves (20a, 20b) are formed in an inner wall of a front bracket (20), and a mold body (26) for insulating and protecting a lead wire (25) is mounted into the grooves (20a, 20b).
US10432053B2
A stator includes an annular stator core, a stator winding, and an insulating sheet member. In the stator core, slots are circumferentially arrayed. The stator winding includes conductor segments having oblique portions formed by open end portions being circumferentially twisted. The open end portions are inserted into the slots from one of two axial-direction sides and extend towards another one. The insulating sheet member is interposed between an inner wall surface of the slot and the conductor segment. The insulating sheet member is rolled into a cylindrical shape along the inner wall surface of the slot, and includes an overlapping portion and a slack portion. In the overlapping portion, two circumferential-direction end portions overlap each other. The overlapping portion is disposed on one of two radial-direction sides of each of the slots. The slack portion is disposed on another one of two radial-direction sides of each of the slots.
US10432051B2
A DC motor includes a cylindrical yoke constituting a magnetic path, pole cores fixed to an inner periphery of the yoke so as to be arranged at even intervals along a circumferential direction of the yoke, and a field conductor that generates a magnetic field to magnetize the pole cores when supplied with a current. The field conductor includes inter-core conductors each of which extends in an axial direction of the yoke so as to be disposed between circumferentially adjacent pole cores. Each of the inter-core conductors is formed by integrating a first conductor part that generates a magnetic field to be applied to one of the circumferentially adjacent pole cores and a second conductor part that generates a magnetic field to be applied to the other of the circumferentially adjacent pole cores.
US10432039B2
A parking assist system is used in a wireless power supply system which performs wireless power supply between a ground-side coil unit and a vehicle-side coil unit. The parking assist system determines a position of a vehicle relative to each of a first region in which the power supply is possible when a gap between the vehicle-side coil unit and the ground-side coil unit is maximum and a second region in which the power supply is possible when the gap is minimum. The parking assist system determines possibility of the power supply, based on a result of the determination on the vehicle position, and displays a result of the determination on the possibility of the power supply, for an occupant of the vehicle.
US10432038B2
Provided are an electronic device and a wireless charging method and apparatus for an electronic device. In the wireless charging method, an environmental parameter transmitted by a wireless charging device is detected (S102); and a receiving antenna board within an electronic device is moved to a designated position according to the environmental parameter, wherein charging efficiency for charging the electronic device at the designated position is higher than charging efficiency for charging the electronic device at other positions (S104). The problems of wasting time and poor user experience caused by adjusting back and forth the electronic device in the process of wireless charging are solved. Free positioning of the antenna can be implemented, and time required by matching the electronic device and a wireless power supply device in the process of wireless charging can be greatly reduced.
US10432035B2
According to one embodiment, a wireless communication device includes a first interface, a first memory, a wireless antenna, a second memory and a second interface. The first interface is capable to electrically connect to a first host device. The first interface communicates with the first host device in accordance with an SD interface. The first memory includes a nonvolatile memory which operates based on power supplied through the first interface from the first host device. The wireless antenna generates power based on a radio wave from a second host device. The second memory is capable to operate based on power generated by the wireless antenna. The second memory has a memory capacity lower than the first memory. The second interface is capable to operate based on power generated by the wireless antenna. The second interface is connected to the second memory and the first interface.
US10432025B2
A power surface or chamber having nearly constant electromagnetic field distribution in 3D comprising at least one primary coil and one primary resonance array made of several coils connected in parallel for generating the electromagnetic field distribution; a single power driver circuit for activating the coils; and a secondary coil and an optional secondary resonance coil to recover the generated electromagnetic field and power up an electric device.
US10432019B2
For each of consumers, a connection control apparatus is provided that includes an opening/closing device capable of connecting or disconnecting an electric power system and a consumer, that, when a power outage occurs in the electric power system, disconnects the electric power system and the consumer from each other by the opening/closing device at a command from an outage management apparatus or the like, and that connects the electric power system and the consumer to each other by the opening/closing device upon receiving a command from the outage management apparatus or the like at the time of restoration from the power outage. A power supply control apparatus supplies electric power from energy provision equipment to electrical appliances during a power outage in the electric power system.
US10432005B2
A system and method for discharging a high voltage vehicle battery. The system includes a discharge circuit having a reference voltage source providing a reference voltage and a load for discharging the battery. A negative terminal of the voltage source is electrically coupled to a negative terminal of the battery so that upon initiation of the discharging sequence, the battery is discharged through the load to the reference voltage. The discharge circuit can be electrically configured so that the battery, the voltage source and the load are electrically coupled in series or the battery, the voltage source and the load are electrically coupled in parallel.
US10432000B2
The disclosure provides a portable charger including a power supply and an adapter. The power supply includes a battery module, a first terminal set, a voltage control module and a first switch portion. The battery module has an initial voltage. The adapter includes a second casing, a second terminal set, an output connector and a second switch portion. When the adapter is detached from the power supply, the portable charger is in a first state, and the voltage control module adjusts the initial voltage to a first voltage, allowing the first terminal set to output the first voltage; when the adapter is disposed on the power supply, the portable charger is in a second state, and the voltage control module adjusts the initial voltage to a second voltage which is different from the first voltage, allowing the first terminal set to output the second voltage.
US10431995B2
An electronic device includes a power supply unit that supplies power received from an external apparatus to the electronic device, a first authentication unit that performs an authentication process for the external apparatus with power supplied from the power supply unit, a second authentication unit that performs an authentication process for a battery with power supplied from the power supply unit when authentication by the first authentication unit has succeeded, and a charging unit that initiates charging the battery with power supplied by the power supply unit when authentication by the second authentication unit has succeeded.
US10431994B2
A self-contained EVCS accessory is electrically engaged to an electric vehicle charging stations to derive one or more operational parameters during the electric vehicle charging process. The self-contained EVCS accessory includes a display unit that can display detailed information to the users regarding the charging process. The EVCS accessory uses its own built-in display unit and power supply to display the detailed information and requires no modification to the charging station. The detailed information, which may include the charging level, charging status, elapsed time, power transferred, cost of power, and the like, may be derived directly by the EVCS accessory or it may be obtained by the accessory from a predefined source of such information. Such an arrangement provides users with much more meaningful information about the charging process compared to the LEDs or light indicators of existing charging stations.
US10431988B2
A system and method for mapping relative positions of a plurality of alternative energy source modules. In one embodiment, the method includes injecting a first contribution current into a power grid by a first alternative energy source module of the plurality of alternative energy source modules and determining an output voltage for each of the plurality of alternative energy source modules. The method also includes constructing a data structure of the relative positions of the plurality of alternative energy source modules employing the output voltage for ones of the plurality of alternative energy source modules.
US10431984B2
The invention relates to a system for generating electric power, comprising: an alternator (1) for coupling with a drive system (7), supplying an AC voltage to an output bus (10); a reversible AC/DC converter (2) in which the AC bus (6) is connected to the output bus (10) of the alternator (1); an electricity-storage element (3) connected to the DC bus (9) of the converter (2); a controller (4) arranged to react to a transient state of load-shedding or charging impact by controlling the converter (2) so as to collect energy on the output bus (10) of the alternator (2) and to store same in the storage element (3) in the case of load-shedding, and to collect energy in the storage element (3) and to inject same into the output bus (10) in the case of charging impact, the converter (2) being controlled so as to inject currents to compensate for harmonic currents into the AC bus (10) of the alternator (1).
US10431981B2
A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units include various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid.
US10431980B2
A method and apparatus for power converter current control. In one embodiment, the method comprises controlling an instantaneous current generated by a power converter that is part of an AC battery such that (i) the power converter appears, from the perspective of an AC line coupled to the power converter, as a virtual AC voltage source in series with a virtual impedance, wherein real and reactive phasor currents for the power converter are indirectly controlled by modifying amplitude and phase of a virtual AC voltage waveform that defines the virtual AC voltage source, and (ii) active power flow is prioritized while the AC battery is operating in a charge mode.
US10431979B2
A method is provided for determining the structure of an electricity transmission grid, including a power supply station including one or more feeders for supplying electrical power to a plurality of electricity consumers, the method including acquiring first data relating to the electrical power consumed by each consumer during various time intervals; acquiring second data relating to the electrical power delivered by each feeder during the various time intervals; generating a plurality of different classes of data; calculating a first selection criteria for each class of data; selecting a first set of classes of data from the classes generated; and determining connection parameters.
US10431978B2
A system and method for conditioning DC power received from hybrid DC power sources is disclosed. A power conversion circuit is coupled to a respective DC power source to selectively condition the output power generated thereby to a DC bus voltage. The power conversion circuit includes a switch arrangement and capacitors arranged to provide a charge balancing in the power conversion circuit. A controller in operable communication with the switch arrangement receives inputs on a DC bus voltage and at least one parameter related to operation of the DC power source, and determines an adjustable voltage to be output from the conversion circuit to the DC bus based on the received inputs. The controller then selectively controls operation of the switch arrangement in order to generate the determined adjustable voltage.
US10431975B2
An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.
US10431973B2
The semiconductor switch control device includes a first FET provided between an anode of a battery and a load and a second FET arranged between a cathode of the battery and the load, in which in a case where a current value that is larger than an abnormal current value indicating that a first drain current flowing through the first FET is an overcurrent and smaller than a maximum current value of the first drain current that can be tolerated by the first FET is set as a current limit value, a limiting gate voltage for setting the current value of the first drain current to a current limit value is applied to the second FET.
US10431972B2
An auto-monitoring circuit including a first input structured to receive a signal from a processor of a circuit interrupter, a second input structured to receive power from a circuit protected by the circuit interrupter, a first switch structured to remain closed while the signal is received at the first input and remains above a predetermined threshold level and to open when the signal ceases to be received at the first input or drops below the predetermined threshold level, a second switch structured to remain open while the first switch is closed and to close when the first switch opens, and an output electrically connected to a trip circuit of the circuit interrupter. Closing the second switch causes a trip signal to be output to the trip circuit that causes the trip circuit to trip open the separable contacts.
US10431965B2
A hydraulic cable puller that includes a hub having an axially-extending annular winding spindle for receiving a plurality of wraps of a rope adapted to connect to a downstream end of a cable to be pulled and to exert a pulling force on the cable. A hydraulic motor is mounted on the hub for rotating the hub and includes an inlet port and outlet port for being attached to inlet and outlet hydraulic supply conduits of a vehicle. A mounting bracket is adapted to mount the hub and the hydraulic motor onto an end of a boom arm of the vehicle.
US10431951B2
A leakage light removal structure 70 is used to remove leakage light in an optical fiber 140 having a core 160, a cladding 162 having a refractive index lower than the core 160, and a covering material 164 having a refractive index higher than the cladding 162. The leakage light removal structure 70 has a fiber housing 72 that houses part of the optical fiber 140, a covering material extension portion 175 covering part of a whole circumference of the cladding 162 by extending part of the covering material 164 along a longitudinal direction of the optical fiber 140 within the fiber housing 72, and a cladding exposure portion 174 in which a portion of the whole circumference of the cladding 162 other than the covering material extension portion 175 is exposed within the fiber housing 72. The covering material 164 may be covered with a resin 76 having a refractive index not more than the refractive index of the covering material 164. For example, the covering material extension portion 175 is formed with a range of angles equal to or less than 180° about an axis of the optical fiber 140 in a cross-section perpendicular to the axis.
US10431946B2
An illustrative electrical harness for bypassing a vehicular security module includes first, second, and third connectors, and electrical conductors. The electrical conductors electrically couple a first pin of the first connector to a third pin of the third connector, a second pin of the first connector to an eleventh pin of the third connector, a first pin of the second connector to a fourteenth pin of the third connector, and a second pin of the second connector to a sixth pin of the third connector. When the first connector is mated with a connector of a first communication bus of a vehicle and the second connector is mated with a connector of a second communication bus of the vehicle, the third connector is configured to bypass the vehicular security module by providing access to a diagnostic port of electrical modules coupled to the first or second communication buses.
US10431944B1
An electric vehicle charging connector assembly comprises a plug connector and a receptacle connector docking with the plug connector. The plug connector includes a first insulating body, a first circuit board, a plurality of contact terminals, a first electrode unit and a first jumper unit. The receptacle connector includes a second insulating body, a second circuit board, a plurality of docking terminals, a second electrode unit and a second jumper unit. The plurality of the contact terminal of the plug connector and the plurality of the docking terminal of the receptacle connector are respectively assembled with the first circuit board and the second circuit board in an elastically embedded manner so as to simplify manufacture procedures, capable of reducing working time and manufacturing cost as well as suitable for quantity production.
US10431940B1
A power receptacle includes a socket, where a direct current (DC) power signal is provided at the socket to provide a DC power to a device that gets plugged into the socket. The power receptacle further includes a switch that is electrically coupled to the socket. The power receptacle also includes a controller that controls the switch to control whether the DC power signal is available at the socket. The controller controls the switch based on a power control command that is wirelessly received by the power receptacle.
US10431922B2
A pin and sleeve device including a contact carrier with captive set screws is disclosed. In some embodiments, the pin and sleeve device includes a housing and a contact carrier. The contact carrier may include a plurality of contact openings each receiving a terminal, such as a pin or a contact sleeve. The contact carrier may include a tool opening or slot extending from an outer surface or perimeter thereof. The tool opening or slot being in communication with one of the contact openings and/or terminals. A set screw may be positioned within the contact openings, the set screw positioned directly adjacent a retainment wall defining an inner portion of the contact openings. The contact carrier may therefore reduce the likelihood that the set screw may be lost or dropped, as the retainment wall is configured to prevent the set screw from passing through or exiting the tool opening or slot.
US10431921B2
Disclosed herein is a sealing cover. The sealing cover includes a cap, a grommet configured to extend from the cap, and a terminal inserted into the grommet, wherein the grommet includes a groove formed to be recessed and having the terminal inserted therein. Advantageous effects are provided such that a process for assembly is simplified and flexibility of terminals is secured.
US10431918B2
Contact pins are provided to a socket main body for accommodating an IC package so as to be in contact with connection terminals of the IC package accommodated in the socket main body. Each contact pin includes a conductive substrate and multiple layers laminated on the surface of the substrate, including: an underlying layer formed on the substrate by Ni plating; a first surface layer formed on the underlying layer by Pd—Ni alloy plating; a second surface layer formed on the first surface layer by Ni plating, thus allowing Sn from the corresponding connection terminal to diffuse into the second surface layer at a rate lower than into a conventional plated Ag layer; and an outermost surface layer formed on the second surface layer by Au plating to serve as an electrical contact layer.
US10431916B2
Housing includes: insertion part into which a connection target is inserted; a plurality of first grooves provided inside insertion part so as to align along an alignment direction being perpendicular to the insertion direction of the connection target, first contact parts being respectively disposed in first grooves; a plurality of second grooves provided inside insertion part so as to oppose to first grooves, second contact parts being respectively disposed in second grooves; first partition wall partitioning adjacent first contact parts; and second partition wall partitioning adjacent second contact parts. At least one of first partition wall and second partition wall has a height dimension in a direction perpendicular to both the insertion direction and the alignment direction, the height dimension being smaller at least at one end in the alignment direction than at a portion between opposite ends in the alignment direction in order to reduce capacitance between contact parts.
US10431913B1
A floating directional support for adjusting a gap between a connecting plate and a joint substrate is provided. The connecting plate is mounted on a substrate. The floating directional support includes a base coupled to the substrate and an insertion member coupled to the connecting plate. The insertion member is movably coupled to the base. The gap between the connecting plate and the substrate is adjusted by moving the insertion member relative to the base.
US10431908B2
Certain embodiments described herein are directed to couplers configured to provide an electrical connection between two or more separate electrical wires. In certain embodiments, the coupler is configured to provide the electrical connection without the two electrical wires physically contacting each other. In other instances, the coupler can be configured to provide an electrical connection between the wires without the use of an electrical box or wiring nuts.
US10431901B2
A surface scattering antenna with a tightly-coupled or tightly-connected array of radiators provides an adjustable antenna with broadband instantaneous bandwidth.
US10431899B2
An apparatus is disclosed herein for a cylindrically fed antenna and method for using the same. In one embodiment, the antenna comprises: an antenna feed to input a cylindrical feed wave; a first layer coupled to the antenna feed and into which the feed wave propagates outwardly and concentrically from the feed; a second layer coupled to the first layer to cause the feed wave to be reflected at edges of the antenna and propagate inwardly through the second layer from the edges of the antenna; and an array of plurality of surface scattering metamaterial antenna elements coupled to the second layer and have slots oriented either +45 degrees or −45 degrees relative to the cylindrical feed wave impinging at a central location of each slot.
US10431896B2
Multiband antenna in the form of a three dimensional solid have a plurality of radiating cavities disposed therein.
US10431893B1
The omnidirectional multiband antenna is a variant on a monocone antenna, particularly including a corrugated extending surface for lowering the low frequency cutoff of the monocone antenna. The omnidirectional multiband antenna includes an electrically conductive conical surface, having a vertex end and a base end, and at least one electrically conductive annular member mounted on the base end. The at least one electrically conductive annular member is formed from a plurality of stacked segments and has a corrugated exterior surface. The vertex end of the electrically conductive conical surface is positioned adjacent to, and spaced apart from, a first surface of a ground plane plate. A plurality of cylindrical rods is provided, a first end of each rod being secured to the at least one electrically conductive annular member, and a second end of each rod being mounted on the first surface of the ground plane plate.
US10431891B2
An antenna arrangement is provided. The antenna arrangement includes a first antenna element and a second antenna element. An inductance coil is coupled to the first antenna element and the second antenna element.
US10431884B2
A radar cover for covering a radar unit which detects a situation around a vehicle, includes: a base portion which serves as a frame; a bright layer which is formed on a surface of the base portion and is a discontinuous metal layer having openings penetrating therethrough in a layer thickness direction; and a transparent top coat layer formed on a surface of the bright layer, parts of the top coat layer being in close contact with the base portion through the openings of the bright layer.
US10431873B2
Embodiments include an antenna assembly comprising a non-conductive housing having an open end; an antenna element positioned inside the non-conductive housing; an electrical cable having a first end electrically coupled to the antenna element and a second end extending out from the open end; one or more dielectric materials positioned inside the non-conductive housing; and a conductive gasket coupled to a portion of the electrical cable positioned adjacent to the open end and outside the non-conductive housing. One embodiment includes a portable wireless bodypack device comprising a frame having a first external sidewall opposite a second external sidewall; a first antenna housing forming a portion of the first sidewall and including a first diversity antenna; and a second antenna housing forming a portion of the second sidewall and including a second diversity antenna. Embodiments also include a method of manufacturing an antenna assembly for a portable wireless bodypack device.
US10431861B2
Proposed is an energy storage device, particularly for use in motor vehicles, comprising at least one base body as well as at least one housing section fixed thereto for accommodating at least one energy storage unit. The energy storage device is characterized by the base body comprising at least one integrated cooling duct for a gaseous medium.
US10431853B2
Energy storage devices, battery cells, and batteries of the present technology may include a housing characterized by a first end and a second end opposite the first end. The housing may include a circumferential indentation proximate the first end. The housing may define a first interior region between the first end and the circumferential indentation, and the housing may define a second interior region between the circumferential indentation and the second end. The batteries may include a set of electrodes located within the housing. The set of electrodes may be positioned within the second interior region of the housing. The batteries may include a cap at least partially contained within the first interior region of the housing. The batteries may also include a first insulator positioned within the housing. The first insulator may extend across the circumferential indentation from the cap to the set of electrodes.
US10431846B2
An energy storage device includes an electrode assembly that includes a sheet-like first electrode and a sheet-like second electrode, the first electrode and the second electrode being alternately layered. Each of the first electrode and the second electrode includes a sheet-like current collecting substrate, and the current collecting substrate of the first electrode is bent toward one side in a layered direction in at least a part of an end portion of the first electrode. The electrode assembly also includes an extension portion formed in such a manner that the current collecting substrate of the second electrode extends outward more than the end portion of the first electrode.
US10431844B2
The invention relates to a method for producing a catalyst coated membrane (19) for a fuel cell (10), wherein the catalyst coated membrane (19) has a membrane (11) and a catalyst layer (12, 13) of a catalytic material arranged on at least one of its flat sides, as well as a nonrectangular active area (20), which is restricted in one direction by two outer sides (30) opposite one another. The method comprises a continuous application of the catalytic material to a membrane material (33) while creating a constant coating width (B) such that an area (35) coated with the catalytic material corresponds to at least the active area (20). A provision is that the membrane material (33) be coated with the catalytic material such that a coating direction (D) has an angle with respect to the opposite outer sides (30) of the active area (20) that is not equal to 90° and not equal to 0°.
US10431836B2
A power supply system includes a fuel cell, a power storage, and a processor. The fuel cell and the power storage supply electric power to a load. The processor is configured to control the fuel cell and the power storage. The processor is configured to acquire a required system power that is required in the power supply system. The processor is configured to determine a power storage shared power such that power efficiency of the electric power supplied from the power storage to the load is equal to or higher than a first value. The processor is configured to determine a fuel cell shared power such that the electric power supplied from the fuel cell is a difference between the power storage shared power and the required system power.
US10431833B2
A method of coating an interconnect for a solid oxide fuel cell includes providing an interconnect including Cr and Fe, and coating an air side of the interconnect with a manganese cobalt oxide spinel coating using a plasma spray process.
US10431826B2
According to the present invention, a nonaqueous electrolyte secondary battery that includes a positive electrode, a negative electrode and a nonaqueous electrolyte is provided. The positive electrode has an operation upper limit potential of 4.3 V or more based on metal lithium and includes a positive electrode active material and an inorganic phosphate compound that has ion conductivity. The inorganic phosphate compound is in a particle state. A ratio of particles having a particle size of 20 μm or more is 1% by volume or less when an entirety of the inorganic phosphate compound is set to 100% by volume. Further, a ratio of particles having a particle size of 10 μm or more may be 10% by volume or less when an entirety of the inorganic phosphate compound is set to 100% by volume.
US10431824B2
In order to provide a negative electrode carbon material capable of providing a lithium secondary battery improved in the capacity and the rate characteristic, there are carried out a first heat treatment of subjecting graphite particles to a heat treatment in an oxidizing atmosphere, and following the first heat treatment, a second heat treatment of subjecting the resulting graphite particles to a heat treatment in an inert gas atmosphere at a higher temperature than in the first heat treatment.
US10431821B2
A cathode active material includes a first cathode material configured of a layered rocksalt type lithium metal oxide, the layered rocksalt type lithium metal oxide including lithium and a metal other than lithium, the metal configured of nickel (Ni), or nickel (Ni) and the like. A site occupancy of metal ions other than lithium at a 3a site obtained by Rietveld analysis of a powder X-ray diffraction pattern of the first cathode material in a cathode in a discharged state is about 5% or less, and a site occupancy of metal ions other than the metal occupying a part of a 3b site at the 3b site is about 1% or over, and the cathode active material is covered with a coating film, and an exposed amount of the cathode active material exposed from the coating film is within a range from about 0.05% to about 8% both inclusive.
US10431813B2
The present disclosure relates to a carbon-silicon composite structure including a carbon particle layer having silicon nanoparticles dispersed therein, a method of preparing the carbon-silicon composite structure, a secondary battery anode material including the carbon-silicon composite structure, and a secondary battery including the secondary battery anode material.
US10431809B2
A battery is provided. The battery includes a positive electrode including a positive electrode active material layer provided on a positive electrode current collector; a negative electrode; and a separator at least including a porous film, wherein the porous film has a porosity ε [%] and an air permeability t [sec/100 cc] which satisfy formulae of: t=a×Ln(ε)−4.02a+100 and −1.87×1010×S−4.96≤a≤−40 wherein S is the area density of the positive electrode active material layer [mg/cm2] and Ln is natural logarithm.
US10431805B2
A separator for a secondary cell includes a porous polymer substrate having a first surface, a second surface opposing the first surface, and a plurality of pores connecting the first surface to the second surface; and heat-resistant coating layers formed on at least one of the first surface and the second surface of the porous polymer substrate and on internal surfaces of the pores using an atomic layer deposition process (ALD). Pores having a non-coated region are present in the internal surfaces of the pores.
US10431800B2
A method for manufacturing busbar modules that includes placing a plurality of first linear conductors on one side and a plurality of second linear conductors on the other side across a long planar conductor, extruding an insulating cover material to cover the first linear conductors and join the first linear conductors to the planar conductor with the insulating cover material and to cover the second linear conductors and join the second linear conductors to the planar conductor with the insulating cover material, cutting the planar conductor along first, second and third cutting lines, forming a first busbar module by joining the first linear conductors and the plurality of busbars, and forming a second busbar module by joining the second linear conductors and the plurality of busbars.
US10431798B2
Provided are a separator for a lithium secondary battery including a substrate and a heat-resistance porous layer disposed on at least one surface of the substrate and including a cross-linked binder, wherein the cross-linked binder has a cross-linking structure of a compound represented by Chemical Formula 2, and a lithium secondary battery including the same.
US10431795B2
The present invention resolves a problem that occurs to a film which is being washed. A film production method of the present invention includes the steps of: (i) passing a heat-resistant separator above rollers located above a washing tank; (ii) lowering another roller into water through a space between the rollers; and (iii) moving at least one of the rollers and the another roller so as to increase a surface area by which the heat-resistant separator is in contact with the another roller.
US10431792B2
A housing having an overpressure protection includes a pressure relief opening with a diaphragm sealing plug to be closed in a fluid-tight manner. The diaphragm sealing plug has a central portion and an angled free peripheral portion. The free peripheral portion in the non-pressurized operating state extends away from the central portion in the direction of the housing external side. The central portion, by way of an increasing housing internal pressure in the axial direction, is deformable in such a manner that the peripheral portion by way of a tension stress that is derived from the deformation of the central portion in a manner proportional to the pressure is releasable from the housing wall in the axial direction in a progressive manner from the inside to the outside such that the diaphragm sealing plug releases the pressure relief opening when a predefined maximum housing internal pressure is reached or exceeded.
US10431786B2
An electricity storage module that includes: a plurality of electricity storage elements each including positive and negative lead terminals protruding outward from end portions thereof; a stack in which the plurality of electricity storage are stacked and adjacent ones of the lead terminals of opposite polarities are connected to each other; bus bars that are individually connected to those of the lead terminals connected in order that are located at opposite ends and that have mutually opposite polarities; and voltage detection terminals that are connected to terminal ends of voltage detection lines and individually connected to the electricity storage elements, wherein the lead terminals, the bus bars, and the voltage detection terminals are collectively connected by laser welding.
US10431783B2
The present disclosure discloses a battery pack that realizes miniaturization and weight reduction by minimizing the number of components of the structure, and that is suitable for pursuing dispersion of external force and structural rigidity using the shape of the structure. The battery pack according to the present disclosure is characterized to include a lower case including both inclined side walls and fixating members facing each other at the both side walls, a battery cartridge disposed between the fixating members in the lower case, and an upper case covering the lower case and the battery cartridge, wherein the battery cartridge contacts the both side walls and the fixating members in the lower case.
US10431782B2
A battery pack includes: a plurality of battery cells arranged in parallel with each other, each of the battery cells comprising an electrode terminal at opposite ends thereof; a holder case configured to accommodate the battery cells; a protection circuit module mounted at an external side of the holder case and comprising a cell voltage measuring terminal facing the holder case; and a connection tab comprising a body part electrically connected to the electrode terminals of a group of the battery cells and an extended part extended from the body part to contact and be electrically connected with the cell voltage measuring terminal of the protection circuit module due to tension in the extended part.
US10431779B2
An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured using the method. The organic layer deposition apparatus includes a conveyer unit including first and second conveyer units, loading and unloading units, and a deposition unit. A transfer unit moves between the first and second conveyer units, and the substrate attached to the transfer unit is spaced from a plurality of organic layer deposition assemblies of the deposition unit while being transferred by the first conveyer unit. The organic layer deposition assemblies include common layer deposition assemblies and pattern layer deposition assemblies.
US10431778B2
An organic light emitting display device is disclosed, which prevents non-uniform luminance and color deviation caused by a change of a viewing angle from occurring. The organic light emitting display device includes a first substrate having a display area and a non-display area; an organic light emitting diode arranged in the display area of the first substrate; and an anisotropic diffusion film arranged on the organic light emitting diode, having a diffusion property varied depending on an incident angle.
US10431777B2
An object of the invention is to provide a novel laminate and a novel image display device which have both of a gas barrier function and a circular polarization conversion function and have a reduced thickness as compared to those in the related art. A laminate of the invention has a substrate, an organic layer A, an inorganic layer B, and an organic layer B in this order, and at least one of the organic layer A or the organic layer B contains a liquid crystal compound.
US10431772B2
A method of manufacturing a display apparatus includes providing a substrate, forming a display unit defining an opening portion in a display region over the substrate, forming a thin film encapsulation layer to seal the display unit, forming a touch electrode over the thin film encapsulation layer, forming a touch insulating film covering the touch electrode such that the thin film encapsulation layer and the touch insulating film are sequentially stacked and formed over the substrate in the opening portion, forming a touch contact hole by removing a portion of the touch insulating film to expose a portion of the touch electrode, and removing a portion of the touch insulating film and a portion of the thin film encapsulation layer formed in the opening portion to expose a portion of the substrate during the forming of the touch contact hole.
US10431767B2
An organic light emitting display device can include an anode electrode disposed on a substrate; an auxiliary electrode disposed on the anode electrode, the auxiliary electrode having a first height and a second height being different from the first height; a bank disposed on one side of the auxiliary electrode and another side of the auxiliary electrode; an organic light emitting layer disposed on an upper surface of the auxiliary electrode in an opening area exposed by the bank; and a cathode electrode disposed on the organic light emitting layer, in which the auxiliary electrode has the first height in a covered area overlapping with the bank and the second height in the opening area exposed by the bank.
US10431765B2
Disclosed are a tandem white organic light emitting diode with long lifespan and low driving voltage, and a display device including the same. The white organic light emitting diode includes a first light emitting part, a second light emitting part and a third light emitting part disposed between a first electrode and a second electrode. The first and third light emitting parts include a blue light emitting layer and the second light emitting part includes a red light emitting layer and a yellow-green light emitting layer. At least one layer of the red light emitting layer and the yellow-green light emitting layer includes a hole transport host based on a compound shown below: wherein each of R1, R2, and R3 are independently selected from hydrogen, heavy hydrogen, a C5-C7 aromatic cyclic and C1-C6 heterocyclic group.
US10431763B2
Provided are a light emitting diode and a preparation method thereof, an array substrate, and an electronic device. The light emitting diode comprises: a substrate, and a first electrode, a quantum rod light emitting layer and a second electrode disposed in lamination on the substrate, wherein, the quantum rod light emitting layer comprises a plurality of quantum rods which present a directional arrangement.
US10431757B2
An electronic or optoelectronic device includes: (1) a semiconductor layer; (2) a dielectric layer in contact with the semiconductor layer and including a polar elastomer; and (3) an electrode. The dielectric layer is disposed between the electrode and the semiconductor layer, and the polar elastomer includes a backbone structure and polar groups that are bonded as side chains to the backbone structure, and each of the polar groups includes 2 or more atoms.
US10431755B2
According to one embodiment, a display device includes an insulating substrate including a first surface on which a plurality of pixels are disposed and a second surface on an opposite side to the first surface, a support substrate disposed on the second surface side of the insulating substrate and an adhesive layer located between the insulating substrate and the support substrate, and the display device includes a display area on which the plurality of pixels are arranged, and an end portion of the adhesive layer is located closer to the display area than an end portion of the insulating substrate.
US10431753B2
The present invention is a substrate for a display, the substrate having a film B including a polysiloxane resin on at least one surface of a film A including a polyimide resin, wherein the film B contains inorganic oxide particles therein, and the present invention has an object to provide a substrate for a display: being able to be applied to a color filter, an organic EL element, or the like without the need to carry out any complex operations; allowing high-definition displays to be manufactured; and being provided with a low CTE, a low birefringence, and flexibility.
US10431749B2
Disclosed is an organic electroluminescent element which is excellent with respect to luminous efficiency and driving voltage and rarely undergoes initial luminance drop. Specifically disclosed is an organic electroluminescent element which comprises, on a substrate, a pair of electrodes composed of an anode and a cathode and a light-emitting layer arranged between the electrodes, and additionally comprises at least one organic layer arranged between the light-emitting layer and the cathode, where in the light-emitting layer contains, for example, a compound (A-1), and the at least one layer arranged between the light-emitting layer and the cathode contains, for example, a compound (e-4).
US10431743B2
A manufacturing method of an OLED anode and display device are provided, which the former method comprises the steps: forming an anode-film layer, a material is an ITO, on a substrate; forming a photoresist-film layer on the anode-film layer; patterning the photoresist-film layer to acquire a photoresist-mask pattern, which comprises: an area of photoresist full-retention, photoresist half-retention, and a photoresist full-removal, wherein the photoresist area of half-retention is located between the full-retention and the full-removal; etching the anode film layer to acquire an anode pattern; removing the photoresist half-retention area; perform a plasma treatment to a portion of the anode pattern outside the photoresist full-retention area by adopting a first gas, comprising at least one of O2, N2O, CF4, Ar; removing the photoresist-mask pattern. The disclosure increases the small thickness portion of brightness to compensate for the display unevenness caused by the thickness difference and improve the display quality.
US10431736B2
A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.
US10431732B2
Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.
US10431729B2
According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.
US10431717B1
Micro LED displays offer brighter screens and wider color gamuts than that achievable using traditional LED or OLED displays. Various embodiments are directed to LED and micro LED structures having substrates comprising a metal and oxygen, such as gallium and oxygen, and methods of forming the same. An integrated circuit (IC) structure can include a substrate comprising a metal and oxygen and a core over the substrate. The core can include a group III semiconductor material and nitrogen, and the core can be doped with n-type or p-type dopants. An active layer comprising indium can be provide on a surface of the core. The indium concentration can be adjusted to tune a peak emission wavelength of the IC structure. The IC structure can include a cladding on a surface of the active layer. The cladding can be doped with dopants of opposite type than those used to dope the core.
US10431716B2
A light-emitting diode includes a first-type nitride region, a light-emitting region and a second-type nitride region, wherein the first-type nitride region includes a plurality of alternating first nitride layers and second nitride layers. The second nitride layers have high-doped emitting points pointing to the corresponding first nitride layer. The second-type nitride region includes a plurality of alternating third nitride layers and fourth nitride layers, wherein doping concentration of the fourth nitride layer is higher than that of the third nitride layer, and the fourth nitride layer has high-doped emitting points pointing to the third nitride layer. By adjusting thickness of the second nitride layer and the fourth nitride layer in different growth cycles, and density and form of corresponding emitting points, horizontal expansion of current in the first-type nitride region and the second-type nitride region can be greatly enhanced through alternating emitting points, thereby improving LED performance.
US10431713B2
A nitride underlayer structure includes a sputtered AlN buffer layer with open band-shaped holes, thus providing a stress release path before the nitride film is grown over the buffer layer. A light-emitting diode with such nitride underlayer structure has improved lattice quality of the nitride underlayer structure and the problem of surface cracks is resolved. A fabrication method of the nitride underlayer includes providing a substrate and forming a band-shaped material layer over the substrate; sputtering an AlN material layer over the band-shaped material layer and the substrate to form a flat film; scanning back and forth from the substrate end with a laser beam to decompose the band-shaped material layer to form a sputtered AlN buffer layer with flat surface and band-shaped holes inside; and forming an AlxIn1-x-yGayN layer (0≤x≤1, 0≤y≤1) over the sputtered AlN buffer layer.
US10431710B2
A light emitting device includes an epitaxial structure. The epitaxial structure includes a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The first type semiconductor layer includes a first semiconductor sublayer. The light emitting layer is disposed between the first type semiconductor layer and the second type semiconductor layer. The first semiconductor sublayer includes a heavily doped part and a lightly doped part which are doped by a first type dopant. A doping concentration of the first type dopant in the heavily doped part is equal to 1018 atoms/cm3 or between 1017 atoms/cm3 and 1018 atoms/cm3. A doping concentration of the first type dopant in the lightly doped part is less than or equal to 1017 atoms/cm3.
US10431701B2
The present disclosure relates to a semiconductor device, an array substrate, and a method for fabricating the semiconductor device. The semiconductor device comprises a substrate, a thin film transistor formed on the substrate, and a first light detection structure adjacent to the thin film transistor, wherein the first light detection structure includes a first bottom electrode, a top electrode, and a first photo-sensing portion disposed between the first bottom electrode and the first top electrode, one of a source electrode and a drain electrode of the thin film transistor is disposed in the same layer as the first bottom electrode of the first light detection structure; the other of the source electrode and the drain electrode of the thin film transistor is used as the first top electrode.
US10431695B2
A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed.
US10431682B2
A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
US10431680B2
A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.
US10431675B1
A carbon nanotube triode apparatus includes a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT) disposed on an electrically insulating thermally conductive substrate. A first contact is disposed on the substrate and electrically coupled to a first end of the HA-SWCNT. A second contact is disposed on the substrate and separated from a second end of the HA-SWCNT by a gap. A gate terminal is coincident with a plane of the substrate.
US10431674B2
A bipolar junction transistor preferably includes: an emitter region; a base region; and a collector region, in which an edge of the emitter region is aligned with an edge of the base region. Preferably, an edge of the base region is aligned with an edge of the collector region, the edge of the emitter region is aligned with the edges of the base region and the collector region, and the widths of the emitter region, the base region, and the collector region are equivalent. According to a top view of the bipolar junction transistor, each of the base region and the collector region includes a rectangle.
US10431673B2
A semiconductor device includes a fin protruding from a substrate and extending in a first direction, source/drain regions on the fin, a recess between the source/drain regions, a device isolation region including a capping layer extending along an inner surface of the recess and a device isolating layer on the capping layer to fill the recess, a dummy gate structure on the device isolation region and including a dummy gate insulating layer, outer spacers on opposite sidewalls of the dummy gate structure, first inner spacers between the dummy gate structure and the outer spacers, and a second inner spacer between the device isolation region and the dummy gate insulating layer.
US10431667B2
Provided is a semiconductor structure. In one or more embodiments of the invention, a semiconductor fin on a substrate is provided. A spacer layer is on a surface of the substrate. A high dielectric constant layer is provided, wherein a first portion of the high dielectric constant layer is on sidewalls of the semiconductor fin, and a second portion of the high dielectric constant layer is over the spacer layer. A work function metal layer is on sidewalls of the semiconductor fin, wherein the work function metal layer has a uniform thickness.
US10431662B2
The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis.
US10431652B2
A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.
US10431651B1
A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.
US10431649B2
According to one embodiment, a semiconductor device includes a first conductive portion, a first extension portion, a first conductive region, a first extension region, a semiconductor portion, and an insulating portion. The first conductive portion includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, and a sixth portion. The first extension portion is electrically connected to the first conductive portion. The first conductive region is provided between the first portion and the second portion, between the third portion and the fourth portion, and between the fifth portion and the sixth portion. The first extension region is electrically connected to the first conductive region. The semiconductor portion includes silicon carbide and includes first to third semiconductor regions. The insulating portion is provided between the first conductive portion and the semiconductor portion and between the first extension portion and the semiconductor portion.
US10431641B2
A thin film transistor (TFT) substrate includes a substrate and a first electrode disposed on the substrate. The first electrode is one of a source electrode and a drain electrode. The TFT further includes a first insulating layer disposed on the first electrode and a second electrode disposed on the first insulating layer. The second electrode is the other one of the source electrode and the drain electrode. The TFT additionally includes a semiconductor layer disposed on the first electrode, the first insulating layer, and the second electrode. The TFT further includes a second insulating layer disposed on the semiconductor layer. The TFT additionally includes a gate electrode disposed on the second insulating layer and overlapping the semiconductor layer. The TFT further includes a pixel electrode that includes a same material as the gate electrode and is electrically connected to the second electrode.
US10431639B2
A display substrate, a manufacturing method thereof, and a display device are provided, and the manufacturing method includes: providing a base substrate; forming a pixel definition layer on the base substrate; oxidizing the pixel definition layer, in which a surface of the pixel definition layer distal to the base substrate is partially oxidized, such that the pixel definition layer includes a main layer proximal to the base substrate and an oxide layer distal to the base substrate; curing and molding the pixel definition layer, and patterning the pixel definition layer to form a pixel definition layer pattern.
US10431632B2
A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (λR) with the longest wavelength of the light with different wavelengths, the optical path length from a reflective electrode to a light-emitting layer (a light-emitting region) included in an EL layer is set to λR/4 and the optical path length from the reflective electrode to a semi-transmissive and semi-reflective electrode is set to λR/2.
US10431623B2
A method applied to a BJT pixel of an image sensor apparatus includes: obtaining at least one of a surface quality signal of a first image sensed by the BJT pixel and a shutter turn-on time corresponding to the first image; and adaptively adjusting a pre-flash time of the BJT pixel for sensing of a second image according to the at least one of the surface quality signal of the first image and the shutter turn-on time corresponding to the first image; wherein the second image follows the first image.
US10431622B2
The present technology relates to a solid-state imaging apparatus and an electronic apparatus that makes it possible to improve coloration and improve image quality. The solid-state imaging apparatus is formed so that, in a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, a first electrical barrier formed between a first photoelectric conversion unit and a first unnecessary electric charge drain unit in the first pixel, and a second electrical barrier formed between a second photoelectric conversion unit and a second unnecessary electric charge drain unit in the second pixel have different heights, respectively. The present technology can be applied to, for example, a CMOS image sensor.
US10431616B2
Methods, systems, apparatus, including computer-readable media storing executable instructions, for color filter arrays for image sensors. In some implementations, an imaging device includes a color filter array arranged to filter incident light. The color filter array has a repeating pattern of color filter elements. The color filter elements include yellow filter elements, green filter elements, and blue filter elements. The imaging device includes an image sensor having photosensitive regions corresponding to the color filter elements. The photosensitive regions are configured to respectively generate electrical signals indicative of intensity of the color-filtered light at the photosensitive regions. The imaging device includes one or more processors configured to generate color image data based on the electrical signals from the photosensitive regions.
US10431612B2
Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. Switches with multiple FET devices having proximity electrodes are also disclosed.
US10431610B2
A panel to detect X-rays includes a plurality of signal lines, a plurality of gate lines, and a plurality of cells in areas adjacent intersections of respective ones of the gate and control lines. A first area includes a first cell having a driving circuit, and a second area includes a second cell which omits a driving circuit. Data lines connected to respective ones of the cells carry signals from which an X-ray image is generated. The second cell may be located in a dummy cell area of the panel.
US10431609B2
An array substrate, a display panel, an encapsulation method for the display panel, and a display apparatus are provided. The array substrate comprises a display region and an encapsulation region divided into a first region away from the display region and a second region adjacent to the display region. The encapsulation region includes a metal layer configured only in the second region, a frit solution layer configured in both the first region and the second region, and a cutting edge configured in the first region. The array substrate which has been aligned and bonded with an encapsulation cover is cut along the cutting edge.
US10431590B2
A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
US10431587B2
A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.
US10431585B2
A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode. The second source/drain region is connected to an edge of the second nanowire.
US10431581B1
Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a well region disposed adjacent to the substrate, a first fin disposed above the well region, a second fin disposed above the substrate, and a gate region disposed adjacent to each of the first fin and the second fin. The semiconductor device may also include at least one third fin disposed above the substrate, a support layer disposed above the at least one third fin, and a compound semiconductor device disposed above the support layer.
US10431572B2
A light emitting device includes: a base comprising a first lead, a second lead, and a supporting member; a light emitting element mounted on the first lead; a protection element mounted on the second lead; a wire including a first end and a second end, wherein the first end is connected to an upper surface of the first lead, and the second end is connected to a first terminal electrode of the protection element; a resin frame located on an upper surface of the base, wherein the resin frame covers at least part of the protection element and surrounds the light emitting element and the first end of the wire; a first resin member surrounded by the resin frame and covering the light emitting element and the first end of the wire; and a second resin member covering the resin frame and the first resin member.
US10431569B2
A method of transferring micro devices is provided. A carrier substrate including a buffer layer and a plurality of micro devices is provided. The buffer layer is located between the carrier substrate and the micro devices. The micro devices are separated from one another and positioned on the carrier substrate through the buffer layer. A receiving substrate contacts the micro devices disposed on the carrier substrate. A temperature of at least one of the carrier substrate and the receiving substrate is changed, so that at least a portion of the micro devices are released from the carrier substrate and transferred onto the receiving substrate. A number of the at least a portion of the micro devices is between 1000 and 2000000.
US10431557B2
The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.
US10431552B2
In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.
US10431550B2
A fan-out electronic component package includes a core, a first electronic component, a first encapsulant, a connection member, a second electronic component, and a second encapsulant. The core member includes a through-hole, wiring layers and vias configured to electrically connect the wiring layers to each other. The first electronic component is disposed in the through-hole, and comprising filters configured to filter different frequency bands. The first encapsulant covers portions of the core member and the first electronic component, and fills portions of the through-hole. The connection member is disposed on the core member and the first electronic component, and includes a redistribution layer electrically connected to the wiring layers and the first electronic component. The second electronic component is disposed on the connection member and electrically connects to the redistribution layer. The second encapsulant is disposed to cover the second electronic component.
US10431549B2
A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
US10431544B2
An interconnect for a semiconductor device includes an insulator layer having a trench. A barrier layer is formed on a surface of the insulator layer in the trench. An elemental cobalt conductor is formed on the barrier layer.
US10431538B2
In accordance with another aspect, a power switch assembly includes a transistor package including a die case, a source bus tab extending from a first side of the die case, a drain bus tab extending from a second side of the die case, a first power bus rail operatively connected to the source bus tab of the transistor package and a second power bus rail operatively connected to the drain bus tab of the transistor package.
US10431536B2
A semiconductor package includes a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate, a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate, and an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip, wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess, in a region overlapped with the lower semiconductor chip, and no electrical signal is applied to the dummy wiring layer.
US10431529B2
A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.
US10431523B2
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
US10431521B2
Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.
US10431518B2
A radio frequency integrated circuit (RFIC) device and a method for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface and a thickness of smaller than 3 μm; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 μm; and a sheet-like heat sink that is formed on the surface of the second dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device.
US10431516B2
A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.
US10431511B2
In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.
US10431488B2
A lift pin passes through a hole of a susceptor on which a wafer is placed inside a process chamber in which an epitaxial process is performed with respect to the wafer, to support the wafer, and has a surface formed of a glassy carbon material.
US10431480B2
A method and apparatus for processing a semiconductor is disclosed herein. In one embodiment, a processing system for semiconductor processing is disclosed. The processing chamber includes two transfer chambers, a processing chamber, and a rotation module. The processing chamber is coupled to the transfer chamber. The rotation module is positioned between the transfer chambers. The rotation module is configured to rotate the substrate. The transfer chambers are configured to transfer the substrate between the processing chamber and the transfer chamber. In another embodiment, a method for processing a substrate on the apparatus is disclosed herein.
US10431472B2
A silicon oxide film or a silicon nitride film is selectively etched by using an etching gas composition including a hydrofluorocarbon that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z≤2x and y≤z are satisfied. Also, a silicon oxide film is etched with high selectivity relative to a silicon nitride film by controlling the ratio among the hydrofluorocarbon, oxygen, argon, etc., included in the hydrofluorocarbon-containing etching gas composition.
US10431459B2
An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed on the upper mask layer. The plurality of preliminary mask patterns is arranged at a first pitch. Two neighboring preliminary mask patterns of the plurality of preliminary mask patterns define a preliminary opening. An ion beam etching process is performed on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns. The first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.
US10431455B2
The interaction between multiple intense ultrashort laser pulses and solids typically produces a regular nanoscale surface corrugation. A coupled mechanism has been identified that operates in a specific range of fluences in GaAs that exhibits transient loss of the imaginary part of the dielectric function and X2, which produces a unique corrugation known as high spatial frequency laser induced periodic surface structures (HSFL). This mechanism is unique in that the corrugation does not involve melting or ablation.
US10431451B2
Certain embodiments herein relate to methods of increasing a reaction chamber batch size. A portion of a batch of wafers is processed within the chamber. The processing results in at least some off-target deposition of material on interior surfaces of the reaction chamber. A mid-batch chamber processing is conducted to stabilize the off-target deposition materials accumulated on the chamber interior surfaces. Another portion of the batch of wafers is processed within the chamber. In various embodiments, processing of the chamber (e.g., mid-batch) and subsequent portion of the batch of wafers is repeated until processing of all wafers is complete. Batch size refers to the number of wafers that may be processed in the reaction chamber between chamber clean cycles. Chamber interior surfaces are seasoned prior to batch processing. Seasoning of the chamber interior surfaces involves applying a coating of the same material that may be used for deposition on the wafers during processing of the same.
US10431450B2
A film forming method for a target object including a main surface and grooves formed in the main surface, includes a step of supplying of a first gas into the processing chamber, and a step of supplying a second gas and a high frequency power for plasma generation into the processing chamber to generate in the processing chamber a plasma of a gas including the second gas in the processing chamber. The first gas contains an oxidizing agent that does not include a hydrogen atom. The second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom. A film containing silicon and oxygen is selectively formed on the main surface of the target object except the grooves.
US10431449B2
Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.
US10431446B2
A wafer cleaner and a method therefor that efficiently cleans a wafer with a little amount of a cleaning liquid and efficiently performs a heating wet cleaning processing. The present invention includes a stage where a wafer is placed, a rotary driving unit that rotates the stage in a circumferential direction, a liquid discharge nozzle disposed facing the wafer placed on the stage and supplies a cleaning liquid on the wafer placed on the stage, and a control unit that causes the liquid discharge nozzle to supply a space between the wafer placed on the stage and the liquid discharge nozzle with a predetermined amount of the cleaning liquid to fill the space. The present invention also includes a lamp disposed on a position facing the wafer placed on the stage to heat at least an interface portion of the wafer and a cleaning liquid.
US10431444B2
The present disclosure provides methods and systems for automated analysis of spectrometry data corresponding to particles of a sample, such as large data sets obtained during single particle mode analysis of an inductively coupled plasma mass spectrometer (SP-ICP-MS). Techniques are presented herein that provide appropriate smoothing for rapid data processing without an accompanying reduction (or with an acceptably negligible reduction) in accuracy and/or precision.
US10431438B2
A high-purity titanium target for sputtering having a purity of 5N5 (99.9995%) or higher, wherein the high-purity titanium target has no macro pattern on the target surface. An object of this invention is to provide a high-quality titanium target for sputtering, in which impurities causing particles and abnormal discharge phenomena are reduced, and which is free from fractures and cracks even during high-rate sputtering, and capable of stabilizing the sputtering characteristics, effectively inhibiting the generation of particles during deposition, and improving the uniformity of deposition.
US10431428B2
In one embodiment, a radio frequency (RF) impedance matching network includes electronically variable capacitors (EVCs), each EVC including discrete capacitors operably coupled in parallel. The discrete capacitors include fine capacitors each having a capacitance value substantially similar to a fine capacitance value, and coarse capacitors each having a capacitance value substantially similar to a coarse capacitance value. The increase of the variable total capacitance of each EVC is achieved by switching in more of the coarse capacitors or more of the fine capacitors than are already switched in without switching out a coarse capacitor that is already switched in.
US10431426B2
A gas plenum arrangement for a substrate processing system includes a gas plenum body arranged to define a gas plenum between a coil and a processing chamber. The coil is arranged outside of an outer edge of the gas plenum body. A plurality of flux attenuating portions is arranged outside of the outer edge of the gas plenum body. The flux attenuation portions overlap the coil.
US10431417B2
In order to provide a sample holder capable of easily searching for an observation field of view, the sample holder includes a sample placement portion including a first top surface on which a counterbore part is formed and a rotational axis for rotating the first top surface horizontally, the counterbore part being aligned by being mounted with a sample supporting member having a pattern for alignment, a sample base portion including an opening through which the sample placement portion is capable of moving vertically and a second top surface around the opening, and a sample cover portion which has conductivity and is pressed down toward a direction of the second top surface of the sample base portion, so that a top surface of the sample supporting member placed on the sample placement portion and the second top surface of the sample base portion are flush with each other.
US10431409B2
An accessory wire retention assembly is for an electrical switching apparatus, such as a circuit breaker. The circuit breaker comprises a housing, separable contacts and an accessory enclosed by the housing, an operating mechanism for opening and closing the separable contacts, and a number of wires adapted to be electrically connected to the accessory. The wires extend from the interior of the housing through an aperture to the exterior. The accessory wire retention assembly includes an insert which cooperates with the housing and to establish a predetermined position of the wires with respect to the accessory and the aperture, and a fastening mechanism which fastens the wires to the insert to maintain the wires in the predetermined position.
US10431404B1
A linkage assembly is provided for guiding movement of a key cap relative to a support board. The linkage assembly includes left and right modular linking members, and a pair of synchronizing units each including a left upper cavity, a left lower cavity, a right upper cavity, and a right lower cavity. In a normal position of the key cap, a left downward abutment region of the left lower cavity is in frictional engagement with a right upward abutment region of the right upper cavity. In a pressed position of the key cap, a left upward abutment region of the left upper cavity is in frictional engagement with a right downward abutment region of the right lower cavity.
US10431401B2
A device and related method temporarily restrict use of a control via one or more of lock out and tag out. The device includes a first and second portion. The first portion has a passageway adapted for the reception of a tie that extends through the first portion along a distance of passageway extension. The second portion has a tang and is movable relative to the first portion to move the tang transversely across the passageway relative to the direction of passageway extension to toggle the device between an opened position and a closed position. A tie may be received in the passageway and the reception of this tie in the passageway may prevent the device from being moved from the closed position back into the opened position due to inability of the tang of the second portion to be moved past the tie in the passageway of the first portion.
US10431400B2
The invention relates to a program switch for mounting on a printed circuit board comprising a housing, an insulator component with contact elements arranged thereon, and a switching element for contacting the contact elements. The housing has at least two connection elements for connecting the program switch to adjacent program switches to form a program switch arrangement having an arbitrary number of poles. Production and stock keeping and sale of the program switch are simple.
US10431398B2
A switch box mechanism of an enclosed switch assembly. The switch box mechanism includes a swivel catch having an elongated body, a pivot configured to allow the swivel catch to rotate relative to an enclosure, and a catch end including a catch configured to engage with an enclosure lid, and a slide feature formed in the elongated body, a rod configured to couple to a switch engagement member that is configured to engage with a rotor of a line base assembly, the rod having a slide portion slidably engaged with the slide feature, and a spring configured to bias the swivel catch. Enclosed switch assemblies and switch subassemblies including the switch box mechanism, and methods of operating enclosed switch assemblies are disclosed, as are other aspects.
US10431395B2
A single device operable as a controller with multiple functions includes a mounting member, a control member, a first switch, a second switch, a third switch, and a processing unit. The control member can be pressed and rotated with respect to the mounting member. The first switch, the second switch, and the third switch are located on the mounting member. The processing unit is electrically connected to all the switches. The processing unit receives a first control signal from the first switch when the control member is pressed, a second control signal from the second switch when the control member is rotated clockwise, and a third control signal from the third switch when the control member is rotated counterclockwise.
US10431388B2
A tunable multilayer capacitor is provided. The capacitor comprises first active electrodes that are in electrical contact with a first active termination and alternating second active electrodes that are in electrical contact with a second active termination. The capacitor also comprises first DC bias electrodes that are in electrical contact with a first DC bias termination and alternating second DC bias electrodes that are in electrical contact with a second DC bias termination. A plurality of dielectric layers are disposed between the alternating first and second active electrodes and between the alternating first and second bias electrodes. At least a portion of the dielectric layers contain a dielectric material that exhibits a variable dielectric constant upon the application of an applied voltage.
US10431383B2
A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the pair external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the external electrodes, wherein a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, is within ±20% of an average of the concentrations of the base metal in the five regions, and thicknesses of the first internal electrode and the second internal electrode are 0.2 μm or greater.
US10431382B2
A printed circuit board (PCB) assembly having several electronic components mounted on a PCB and a damping layer covering the electronic components, is disclosed. Embodiments of the PCB assembly include an overmold layer constraining the damping layer against the PCB. Embodiments of the PCB assembly include an interposer between a capacitor of the electronic components and the PCB. Other embodiments are also described and claimed.
US10431375B2
A hardened inductive device and systems and methods for protecting the inductive device from impact is provided. The inductive device is hardened with protective coating and/or an armor steel housing. The hardened inductive device is protected from impact by an object such as a bullet and leakage of dielectric fluid is prevented. Acoustic and vibration sensors are provided to detect the presence and impact, respectively, of an object in relation to the inductive device housing. The measurements of the acoustic and vibration sensors are compared to thresholds for sending alarms to the network control center and initiating shut-down and other sequences to protect the active part. The acoustic sensor results are utilized to determine the location of origin of the projectile.
US10431371B2
A method of forming an inductor assembly includes depositing a magnetic core on a planar substrate lying in a core plane, forming an inductor coil that generates a magnetic field that passes through the magnetic core in a closed loop parallel to the core plane, and annealing the magnetic core while applying an external magnetic field that passes through the magnetic core in a radial direction to permanently fix the easy axis of magnetization parallel to the radial direction. As a result, the hard axis of magnetization of the magnetic core is permanently oriented in a generally circular closed path parallel to the closed loop of the inductor's magnetic field.
US10431365B2
An electronic component includes a main body made from a metal magnetic powder and an insulating resin, a coating film covering the surface of the main body, a conductor disposed inside the main body, inorganic particles adhering to the surface of the coating film, and outer electrodes which are electrically connected to the conductor and which cover portions of the surface of the coating film while inorganic particles adhere to the portions, wherein the coating film contains a resin and metal cations.
US10431361B2
This disclosure includes magnetic field correction devices and methods for using the same. In particular, some magnetic field corrections devices include an arch-shaped body configured to be worn outside of a user's mouth such that the arch-shaped body follows a contour of the user's face; and where the arch-shaped body comprises one or more sidewalls configured to be coupled to a plurality of members comprising magnetically permeable material. Other embodiments employ a forehead support, frame, and one or more straps coupled to an arch-shaped body. Other embodiments employ a hybrid of intraoral and external embodiments.
US10431357B2
Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material; a first contact coupled to the first doped region; a second contact opposite the first contact coupled to the second doped region; and an isolation trench to circumscribe the third doped region.
US10431346B2
The purpose of the present invention is to provide: a radiation shielding liquid filter having a radiation shielding effect, a simpler and lighter structure, and various mounting locations so as to protect a surgical patient from exposure to radiation emitted during X-ray imaging using a C-arm, which is a mobile X-ray imaging device, and a stationary X-ray imaging device used during X-ray imaging in a hospital; and an X-ray imaging device provided with the same.
US10431344B2
An assembly is provided that includes a device for locking tubes in position relative to one another, with at least a first arm, a locking axle having a plurality of bearing surfaces, the locking axle being movable between a position locking the tubes each between one of said bearing surfaces and the first arm, and a released position, in which the tube segments are free.
US10431341B2
The invention provides a detection device, method, and program capable of highly accurately detecting a pre-disease state that indicates a precursor to a state transition from a healthy state to a disease state. The following processes are carried out: a process of obtaining measured data on genes, proteins, etc. related to a biological object as high-throughput data (s1), a process of selecting differential biological molecules (s2), a process of calculating the SNE of a local network (s3), a process of selecting a biomarker candidate (s4), a process of calculating an average SNE across the entire network (s5), and a process of determining and detecting whether or not the system is in a pre-disease state (s6).
US10431338B2
System, method, and computer program product for evaluating attribute values to determine treatment eligibility, the method by receiving a set of required attributes associated with a treatment protocol, receiving a case, wherein the case includes a patient history containing patient attribute values, identifying a patient attribute value that does not satisfy a required attribute specified by the treatment protocol, determining a likelihood that the patient could meet the required attribute based upon the patient history, and providing an indication of the likelihood that the patient could satisfy the required attribute specified by the treatment protocol.
US10431332B2
There are provided a medical assistance device, an operation method of a medical assistance device, a non-transitory computer-readable recording medium, and a medical assistance system allowing a user to use a diagnostic assistance program with confidence. A comparison determination unit compares a designated data range, which is designated as a range to be used for input data of a diagnostic assistance program, with a recommended data range, which is set for each diagnostic assistance program and is recommended as a range to be used for input data. The comparison determination unit outputs information regarding surplus data, which is data outside the recommended data range in the designated data range, and information regarding missing data, which is data outside the designated data range in the recommended data range. A difference information output unit outputs the information of the surplus data or the missing data as difference information.
US10431323B2
A memory system includes a calibration engine, a memory, and a memory controller coupled to the memory by a channel used to transmit a plurality of commands from the memory controller to the memory. The memory controller estimates a total energy consumed based on the first plurality of commands in a first sampling period and determines a first temperature change of the memory based on the first total energy consumed. The memory controller transmits an impedance calibration command to the calibration engine if the first temperature change of the memory exceeds a first threshold. The calibration engine changes an impedance of an I/O terminal of the memory based on the calibration command.
US10431317B2
A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.
US10431311B2
According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.
US10431307B2
An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.
US10431301B2
Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
US10431298B2
According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
US10431295B2
A static random access memory (SRAM) that includes a memory cell comprising at least two p-type pass gates. The SRAM also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell.
US10431294B2
Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.
US10431293B1
An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.
US10431292B2
Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.
US10431291B1
A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.
US10431278B2
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.
US10431275B2
A magnetic apparatus, a memory using the magnetic apparatus and method for providing the magnetic apparatus are described. The magnetic apparatus includes a magnetic junction and a hybrid capping layer adjacent to the magnetic junction. The hybrid capping layer includes an insulating layer, a discontinuous oxide layer, and a noble metal layer. The discontinuous oxide layer is between the insulating layer and the noble metal layer. The insulating layer is between the magnetic junction and the noble metal layer. In one aspect, the magnetic junction includes a reference layer, a nonmagnetic spacer layer that may be a tunneling barrier layer and a free layer.
US10431272B2
Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.
US10431264B2
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
US10431263B2
Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.
US10431256B2
Methods, apparatuses and systems for detecting defective sectors on a recording medium. A defective sector detector apparatus comprises an error-corrected ECC symbol number calculator and a defective sector determination unit. The error-corrected ECC symbol number calculator is configured to count a total number of error correcting code (“ECC”) symbols that are error-corrected in data read from data sectors on a track of a recording medium of the storage device. The defective sector determination unit is configured to receive the total number of ECC symbols that are error-corrected for a data sector from the error-corrected ECC symbol number calculator and determine whether the total number of ECC symbols that are error-corrected exceeds a threshold value. If it is determined that the total number of ECC symbols that are error-corrected exceeds the threshold value, the defective sector determination unit outputs information indicating the data sector to be a defective sector.
US10431248B2
A magnetic tape includes a non-magnetic layer including non-magnetic powder and a binder on a non-magnetic support; and a magnetic layer including ferromagnetic powder and a binder on the non-magnetic layer. The magnetic layer includes a timing-based servo pattern. The center line average surface roughness Ra measured regarding the surface of the magnetic layer is less than or equal to 1.8 nm. One or more components selected from a fatty acid and a fatty acid amide are included in at least the magnetic layer, and the C—H derived C concentration calculated from the C—H peak area ratio of C1s spectra obtained by X-ray photoelectron spectroscopic analysis performed on the surface of the magnetic layer at a photoelectron take-off angle of 10 degrees is greater than or equal to 45 atom %.
US10431243B2
This invention provides a signal processing apparatus for improving the speech determination accuracy in an input sound. The signal processing apparatus includes a transformer that transforms an input signal into an amplitude component signal in a frequency domain, a calculator that calculates a norm of a change in the amplitude component signal in a frequency direction, an accumulator that accumulates the norm of the change in the amplitude component signal in the frequency direction calculated by the calculator, and an analyzer that analyzes speech in the input signal in accordance with an accumulated value of the norm of the change in the amplitude component signal in the frequency direction calculated by the accumulator.
US10431233B2
Methods, an encoder and a decoder are configured for transition between frames with different internal sampling rates. Linear predictive (LP) filter parameters are converted from a sampling rate S1 to a sampling rate S2. A power spectrum of a LP synthesis filter is computed, at the sampling rate S1, using the LP filter parameters. The power spectrum of the LP synthesis filter is modified to convert it from the sampling rate S1 to the sampling rate S2. The modified power spectrum of the LP synthesis filter is inverse transformed to determine autocorrelations of the LP synthesis filter at the sampling rate S2. The autocorrelations are used to compute the LP filter parameters at the sampling rate S2.
US10431229B2
A signal processing device, method, and program that may obtain audio at a higher audio quality when decoding an audio signal. An envelope information generating unit generates envelope information representing an envelope form of high frequency components of an audio signal to be encoded. A sine wave information generating unit extracts a sine wave signal from the high frequency components of the audio signal, and generates a sine wave information representing an emergence start position of the sine wave signal. An encoding stream generating unit multiplexes the envelope information, the sine wave information, and low frequency components of the audio signal that have been encoded, and outputs an encoding stream obtained as the result. The high frequency components included in the sine wave signal may be predicted at a higher accuracy from the envelope information and the sine wave information at the receiving side of the encoding stream.
US10431227B2
A multi-channel audio decoder for providing at least two output audio signals on the basis of an encoded representation is configured to render a plurality of decoded audio signals, which are obtained on the basis of the encoded representation, in dependence on one or more rendering parameters, to obtain a plurality of rendered audio signals. The multi-channel audio decoder is configured to derive one or more decorrelated audio signals from the rendered audio signals, and to combine the rendered audio signals, or a scaled version thereof, with the one or more decorrelated audio signals, to obtain the output audio signals. A multi-channel audio encoder provides a decorrelation method parameter to control an audio decoder.
US10431217B2
Synchronized output of audio on a group of devices comprises sending audio data from an audio distribution master device to one or more slave devices in the group. In group mode, a slave can be configured to receive audio data directly from a master device acting as a soft wireless access point (WAP) in an environment that includes a traditional WAP. In response to a user request to output audio via the slave in individual mode, the slave may be configured to dynamically switch to receiving audio data via the WAP in the environment without routing the audio data through the master device acting as the soft WAP. This dynamic switching to receiving audio data via the WAP in individual mode can reduce bandwidth consumption on the master device.
US10431215B2
A system and method is provided for adjusting natural language conversations between a human user and a computer based on the human user's cognitive state and/or situational state, particularly when the user is operating a vehicle. The system may disengage in conversation with the user (e.g., the driver) or take other actions based on various situational and/or user states. For example, the system may disengage conversation when the system detects that the driving situation is complex (e.g., car merging onto a highway, turning right with multiple pedestrians trying to cross, etc.). The system may (in addition or instead) sense the user's cognitive load and disengage conversation based on the cognitive load. The system may alter its personality (e.g. by engaging in mentally non-taxing conversations such as telling jokes based on situational and/or user states.
US10431210B1
A whole sentence recurrent neural network (RNN) language model (LM) is provided for for estimating a probability of likelihood of each whole sentence processed by natural language processing being correct. A noise contrastive estimation sampler is applied against at least one entire sentence from a corpus of multiple sentences to generate at least one incorrect sentence. The whole sentence RNN LN is trained, using the at least one entire sentence from the corpus and the at least one incorrect sentence, to distinguish the at least one entire sentence as correct. The whole sentence recurrent neural network language model is applied to estimate the probability of likelihood of each whole sentence processed by natural language processing being correct.
US10431208B2
Techniques are described herein for optimizing the presentation of content through obtaining viewership metrics, generating multiple renditions of presentations of content, and selecting optimized renditions of content. One aspect includes associating a request for viewership metrics with a presentation of content, publishing the presentation of content, and receiving information of the viewership metrics associated with the presentation. Another aspect includes copying a presentation of a content item, creating a second presentation of the content item for publishing over one or more channels, and linking the presentation of the content item to the second presentation of the content item, such that a change to one propagates to the other of the presentation of the content item or the second presentation of the content item. In yet another aspect, a content rendition may be selected for presentation based on performance of the rendition out of multiple renditions in an auction.
US10431206B2
Methods, systems, and apparatus, including computer programs encoded on computer storage media for training a hierarchical recurrent neural network (HRNN) having a plurality of parameters on a plurality of training acoustic sequences to generate phoneme representations of received acoustic sequences. One method includes, for each of the received training acoustic sequences: processing the received acoustic sequence in accordance with current values of the parameters of the HRNN to generate a predicted grapheme representation of the received acoustic sequence; processing an intermediate output generated by an intermediate layer of the HRNN during the processing of the received acoustic sequence to generate one or more predicted phoneme representations of the received acoustic sequence; and adjusting the current values of the parameters of the HRNN based at (i) the predicted grapheme representation and (ii) the one or more predicted phoneme representations.
US10431203B2
Training a machine by a machine learning technique for recognizing speech utterance to determine language fluency level of a user. Native speaker recorded data and language specific dictionary of heteronyms may be retrieved. The native speaker recorded data may be parsed and the heteronyms from the native speaker recorded data may be isolated. Linguistic features from the native speaker recorded data including at least linguistic features associated with the heteronyms may be extracted, and a language dependent machine learning model is generated based on the linguistic features.
US10431202B2
Examples of the present disclosure describe systems and methods relating to conversation state management using frame tracking. In an example, a frame may represent one or more constraints (e.g., parameters, variables, or other information) received from or generated as a result of interactions with a user. Consequently, each frame may represent one or more states of an ongoing conversation. When the user provides new or different information, a new frame may be created to represent the now-current state of the conversation. The previous frame may be retained for later access by what is referred to herein as a “dialog agent,” which is the portion of the system that can search and use previous state-related information. When an utterance is received, a frame to which the utterance relates may be identified. Thus, the dialog agent may track multiple states simultaneously, thereby enabling conversation features that were not previously possible.
US10431173B2
A drive circuit includes: a connection module, including a first and a second interfaces for receiving a control signal; an adjustment module, including: a first switch, a control end thereof is coupled to the first interface, a first end is coupled to a supply voltage, and a second end is coupled to a first resistor; second switch, a control end thereof is coupled to the second interface, a first end is coupled to a second resistor, and a second end is grounded; and a third resistor, coupled to the first and the second switches; and a write protection module coupled to the second end of the second switch, and including a software written and a write protection states, where the first and the second switches are controlled to be open or closed by using the control signal, to control the working states of the write protection module.
US10431171B2
A method includes applying a common voltage to a display panel, digitally converting a feedback common voltage from the display panel, detecting an effective ripple signal exceeding a reference value based on the digitally converted feedback common voltage, comparing a total number of effective ripple signals detected during a first frame period with a threshold value, determining whether the effective ripple signals of the first frame period are crosstalk inducing signals based on a comparison result, and determining whether to change a polarity pattern of image data signals to be applied to the display panel during a second frame period based on a determination result in terms of the crosstalk inducing signal.
US10431168B2
The present invention provides driving methods for a color display device in which each pixel can display four high-quality color states. More specifically, an electrophoretic fluid is provided which comprises four types of particles, dispersed in a solvent or solvent mixture.
US10431165B2
A display apparatus includes a timing controller configured to convert input image data into a hue, saturation, brightness (HSV) color space to generate a saturation histogram, generate a saturation gain curve and a dimming value based on the saturation histogram, control saturation of an input image based on the saturation gain curve to generate a data signal, and control luminance of the input image based on the dimming value to generate a light source control signal. A data driver is configured to generate data voltages based on the data signal. display panel is configured to display an output image based on the data voltages. A light source is configured to provide light to the display panel based on the light source control signal.
US10431164B2
A display device with low power consumption is provided. A display device having high visibility regardless of the ambient brightness is provided. The display device includes a light-receiving element, a display element, a first transistor, and a second transistor. One of a source and a drain of the first transistor is electrically connected to one electrode of the light-receiving element. The one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The display device has a function of, by turning on the second transistor, changing the gray level of the display element in accordance with the amount of light detected by the light-receiving element.
US10431160B2
An organic light emitting diode panel, a gate driver circuit and a gate driver circuit unit are disclosed, where the gate driver circuit includes a scanning signal generating unit for generating a scanning signal, transmitting a first clock signal to a scanning signal output terminal under the control of a pulse signal, and pulling down and maintaining the voltage of the scanning signal output terminal at a low voltage level under the control of a second clock signal. The gate driver circuit unit also includes a light emitting signal generating unit for generating a light emitting signal, pulling down the voltage of the light emitting signal output terminal under the control of the pulse signal, and charging the light emitting signal output terminal under the control of the second clock signal.
US10431159B2
A register circuit includes an output circuit and an input circuit. The output circuit includes a first transistor and a second transistor. The first transistor is provided in a first electrically-conductive path between a first control terminal and an output terminal. The second transistor is provided in a second electrically-conductive path between a first power terminal and the output terminal. The input circuit includes a third transistor and a fourth transistor. The third transistor is provided in a third electrically-conductive path between an input terminal and a gate terminal of the first transistor. The fourth transistor is provided in a fourth electrically-conductive path between a second control terminal and a gate terminal of the third transistor and has a gate terminal that is coupled to the input terminal.
US10431154B2
An organic light-emitting diode display may contain an array of display pixels. Each display pixel may have a respective organic light-emitting diode that is controlled by a drive transistor. At low temperatures, it may be necessary to increase the amount of current through an organic light-emitting diode to achieve a desired luminance level. In order to increase the current through the light-emitting diode, the ground voltage level may be lowered. However, this may lead to thin-film transistors within the pixel leaking, which may result in undesirable display artifacts such as bright dots being displayed in a dark image. In order to prevent leakage in the transistors, the transistors may be coupled to separate reference voltage supplies or separate control lines. Additionally, the transistors may be positioned to minimize leakage even at low ground voltage levels.
US10431153B2
The disclosure discloses a pixel circuit, a method for driving the same, and an organic electroluminescent display panel, where the pixel circuit includes a node initialization module and a drive control module, the node initialization module includes a first switch transistor with a gate electrically connected with a first scan signal terminal, a source electrically connected with a first reference signal terminal, and a drain electrically connected with a first node; and a seventh switch transistor with a gate electrically connected with the first scan signal terminal, a source electrically connected with the second reference signal terminal, and a drain electrically connected with the second node; the drive control module includes a drive transistor with a gate electrically connected with the first node, a source electrically connected with the second node.
US10431149B2
A display apparatus is provided. The display apparatus includes a display including a plurality of display modules, and a processor configured to measure a first voltage according to a current flowing through reference pixels operating in a light reception mode by a light emitted from first adjacent pixels, to measure a second voltage according to a current flowing through reference pixels operating in the light reception mode by a light emitted from second adjacent pixels, and in response to a difference between the measured voltages is larger than or equal to a predetermined threshold value, to adjust a gain with respect to the second adjacent pixels based on amplitudes of the first voltage and the second voltage, and the first adjacent pixels are included in a different display module from the second adjacent pixels.
US10431143B2
A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.
US10431140B2
A display device includes a display unit including pixels coupled to scan lines and data lines, a data driver which supplies a data signal to pixels through the data lines, a scan driver which generates a scan signal using a first scan voltage and a second scan voltage, and supplying the scan signal to the pixels through the scan lines, a processor which generates first scan voltage information by setting a first scan voltage level, based on an ambient temperature of the display device, a timing controller which generates a power control signal using the first scan voltage information and delta voltage information, and a power supply which generates the first scan voltage and a delta voltage using the power control signal, and generates the second scan voltage by dropping the delta voltage from the first scan voltage.
US10431134B2
A display device includes a driver for a display panel. The display panel includes a first area and a second area that includes a plurality of pixels. The driver includes a master driver and a slave driver. The master driver compensates a first image signal for the first area to generate a first compensation signal based on the first image signal and a second image signal for the second area. A first data signal corresponding to the first compensation signal and a scan control signal a provided to the first area. The slave driver compensates the second image signal to generate a second compensation signal based on the first image signal and the second image signal. A second data signal corresponding to the second compensation signal and the scan control signal are provided to the second area.
US10431132B2
A method for characterizing and eliminating the effect of propagation delay on data and monitor lines of AMOLED panels is introduced. A similar technique may be utilized to cancel the effect of incomplete settling of select lines that control the write and read switches of pixels on a row.
US10431129B2
Provided is an information processing device wherein, in a first state where a first side face and a second side face are disposed facing each other, a support member can be fitted into a first opening and a second opening and fixed.
US10431127B2
This invention is referred to a guarantee seal for non-opening electrical energy consumption meters with mechanical seal type padlock, disposable of a single use; for sealing or closing some container, box, door, cabinet, meter, valve, pump, bag, carrier bag, water tank, etc., meanly used for the electricity meters commonly used in countries of North America, Central and South America; whose purpose is protecting and controlling the electricity theft, guarantying its immobility. Such guarantee seal has a unique shape that fits exactly with the cavities of the meters and it gets in by pressure, therefore if the seal is located outside of such cavity its external manipulation is evident, furthermore, it has a lid, a base, a verification system by continuity and tag or RFID tag to ensure the integrity of such seal.
US10431122B2
A method is provided for setting, by a processor, a minimum and maximum symbol size for rendering at different zoom levels on a digital map. In another embodiment of the invention, the size of overlay features, such as line widths, received by a processor is automatically adjusted for different zoom levels depending on the average size of map features, such as polygons. In one example, line widths are decreased, and/or made partially transparent, as the map views are zoomed out, finally being altogether eliminated. In one embodiment, the system automatically analyzes received data to determine an appropriate way to map the data.
US10431121B2
This invention involves a balance scale with a base, a balance arm support, a balance arm, a pointer, and a movable label plate containing descriptions. The balance arm has a tray on each end, where one tray holds an article representing mankind with sin, and the other tray holds an article representing the redemptive work of Jesus Christ. The articles on each tray are of equal or approximately equal weight. The scale rotates when the weight of the articles are added to or removed from the trays, and the scale rotation will determine which description the pointer will point to. This invention can be used as a Christian teaching aid showing the benefit of choosing to accept the death of Christ as payment in full for our sins, along with showing the consequence of our refusal to accept the death of Christ as payment for our sins.
US10431119B2
Braille cells and assemblies include an actuator that engages and makes readable a Braille dot by moving a shaft on a base to engage the dot. An electro-permanent magnet and a separate magnetic plate on the shaft can cause the rotation. By running an electric pulse through the electro-permanent magnet, it will rotate the shaft about a pivot under attraction to the magnetic plate. The shaft then engages tactile with the Braille dot to make it and potentially other dots form a Braille character. An electric pulse in an opposite direction may cause the magnetic field to cease and the tactile pin to disengage. The electro-permanent magnet may be coupled a mesh of rows and columns each with a P-channel MOSFET and N-channel MOSFET on opposite ends. The magnet may be at an intersection of a row and a column with diodes, which may be Zenner diodes.
US10431118B2
Braille cells and assemblies include an actuator that engages and makes readable a Braille dot by rotating about a hinge on a base to engage the dot. An electro-permanent magnet on the rod and a magnetic plate on the underlying base can cause the rotation. By running an electric pulse through the electro-permanent magnet, it will rotate the rod about the pivot hinge under attraction to the magnetic plate at the other end of the base. The rod then engages with a tactile pin contacting the Braille dot and making it readable. An electric pulse in an opposite direction may cause the magnetic field to cease and the tactile pin to disengage. The electro-permanent magnet may be coupled a mesh of rows and columns each with a P-channel MOSFET and N-channel MOSFET on opposite ends. The magnet may be at an intersection of a row and a column with diodes.
US10431112B2
Computer-based systems and methods support linguistic education between a tutor and a student using mobile computing devices with touchscreen user interfaces for both that allow the tutor to deliver lesson prompts and monitor in real-time, on his/her mobile device, responses made by the student on the student's mobile device. The linguistic lessons can be quickly created and individualized for each student, based on statistical estimates of student knowledge of each concept in the appropriate scope and sequence. The planned lesson may then be downloaded onto the tutor's mobile device for delivery in a tutoring session. The tutor uses the touchscreen interface of the tutor mobile device to select concept prompts in the downloaded lesson. These prompts can then be displayed on the student's input device. The student may use an input component of the student mobile device to enter a response that is then transmitted back to the tutor mobile device. The student may also answer orally. The tutor, through the touchscreen interface of the tutor mobile device, records correctness and the required hint level for each student response given during a lesson. These records can then be uploaded to the host computer system and used to update a Student Model after the lesson is complete. After it is updated, the Student Model can be used to plan the next lesson for that student.
US10431111B2
A remedial handwriting aid. The remedial handwriting aid includes a glove. The glove includes a first connector attached to a pinky sleeve and second connector attached to a ring finger sleeve. A third connector is attached to a palm portion of the glove. The first connector and the second connector releasably attach to the third connector.
US10431107B2
A device for providing feedback includes an imaging device configured to capture an image of a subject, a feedback device, and a controller communicatively coupled to the imaging device and the feedback device. The controller includes at least one processor and at least one memory storing computer readable and executable instructions that, when executed by the processor, cause the controller to determine one or more identifying characteristics of the subject, set one or more parameters for determining a facial expression of the subject in the image based on the one or more identifying characteristics of the subject, determine the facial expression of the subject in the image based on the one or more parameters, and provide the feedback with the feedback device based on the determined facial expression.
US10431100B2
A flight planning system is disclosed for providing an interactive and customizable flight planning tool. The flight planning system may include a memory device for storing flight information and one or more hardware processors. The processors may receive, from a client device associated with the flight planning system, a first flight information request and provide, in response to the first flight information request, an interactive user interface having a graphical representation of a flight plan that includes at least a flight route. The processors may provide a plurality of selectable overlays that modify the appearance of the graphical representation and display additional information related to the flight information. The processors may receive a second request related to the flight information and provide a modified user interface comprising at least a feature related to the second request and the flight information.
US10431097B2
A handheld, portable device is used to facilitate inspection of vehicles, by generating an electronic vehicle inspection record that can be used by fleet operators to provide evidence of complying with required vehicle inspections. When the vehicle inspection record is generated, route identification data is added to the inspection record. The route identification data defines which of a plurality of predefined routes the vehicle has serviced, or will service, during a time period proximate the inspection of the vehicle. Fleet operators can thus use archived inspection records as evidence of compliance with inspection requirements, and to document what route a vehicle serviced at a particular time.
US10431093B2
One general aspect of the present disclosure includes a method for warning of collision avoidance. The method may include receiving, with at least one server, position and movement information from a remote client, forming a motion model of the client including a predicted position of the client at a future time, and determining whether an object will be in a proximity of the position of the client at the time. If the object will be in the proximity of the position of the client at the time, the method may include determining a probability of a collision between the client and the object at the time. If the probability meets a threshold, the method may include transmitting a collision avoidance signal to at least one of the client and the object.
US10431076B2
A smart crosswalk safety system for a pedestrian comprises bollard devices disposed in a sidewalk, each bollard device including a pedestrian identification sensor detecting a pedestrian, a camera photographing an area including the crosswalk, a beacon device transmitting a beacon signal toward the crosswalk when an operation signal is received from a control device, the control device generating an operation signal to drive the beacon device when the bollard device identifies a pedestrian who walks from the sidewalk toward the crosswalk and a pedestrian is identified to be present in the pedestrian identification area of an image captured by the camera, and a lock screen application installed in the pedestrian terminal of a pedestrian who crosses a street at the crosswalk to change screen of the terminal to a locked state when a beacon signal is received.
US10431069B2
An apparatus for providing an object loss prevention service in a vehicle, and which includes a sensor unit configured to sense an in-vehicle object of a passenger inside the vehicle; and a processor configured to display in-vehicle object state information including at least one of a position of the object and a type of the object, and output an alarm indicating the object has been left in the vehicle in response to the passenger getting out of the vehicle.
US10431067B2
An apparatus for protecting an entrance to a protected area comprises a magnetic sensor to measure an ambient magnetic field or gradient within a first zone of sensitivity at a non-magnetic sensor means adapted to detect the presence of objects within a primary detection zone, a signal processing circuit arranged in communication with the magnetic sensor apparatus and non-magnetic sensor apparatus, and a warning device operable by an output signal from the signal processing circuit, the warning device adapted to provide an alarm. The signal processing circuit identifies temporal variations due to the movement of a ferromagnetic object within the ambient magnetic field and correlates them with instances in which the non-magnetic sensor means detects the presence of an object in its detection zone, and causes the alarm to operate in the event that the correlation is indicative of the presence of a ferromagnetic object in the primary detection zone. It also determines the direction from which an object is approaching the using signals from the non-magnetic sensor means and modifies the operation of the warning device dependent on the direction.
US10431066B2
A terminal apparatus and method therefor according to the present invention are an apparatus and method for receiving and displaying monitoring information in an object monitoring system for sensing and monitoring an object, have a plurality of operation modes including a condition check mode of checking a condition of the object until receiving an intention to actually perform an action on the object after receiving the monitoring information, and prohibit executing the condition check mode on the object when a condition of the object is being checked by other apparatus in the condition check mode. The present invention relates to an object monitoring system using the terminal apparatuses, and a central processing apparatus and central processing method therefor.
US10431057B2
A haptic conversion system is provided that intercepts frames of audio data, such as a digital audio signal, converts the frames into a haptic signal, and plays the created haptic signal through an actuator to produce haptic effects. The haptic signal is based on a maximum value of each audio data frame, which defines a magnitude of the haptic signal. The haptic signal is applied to the actuator configured to receive the haptic signal, where the actuator utilizes the haptic signal to generate the one or more haptic effects.
US10431049B2
A method for implementing an augmented reality lottery game on a player's mobile device includes providing lottery tickets with a code for entry into the augmented reality game. A common game server communicates with the mobile devices, and a player enters and transmits the code via the mobile device to initiate the augmented reality game. The game server receives real-world location data from the mobile device and transmits participating establishment locations to the mobile device within a predefined distance of the player's location. Upon verifying the player's location, the game server enables an overlay of virtual objects on a screen image on the player's mobile device of the establishment location. The mobile device provides instructions to the player for interacting with the virtual object in accordance with the augmented reality game.
US10431045B2
A game apparatus includes a symbol arrangement device, a replacement symbol drawing device, a symbol replacement device, and a win determination device. The symbol arrangement device is configured to arrange a plurality of symbols in a predefined area. The replacement symbol drawing device is configured to draw at least one replacement target symbol to be replaced. The symbol replacement device is configured to replace, with at least alternative symbol, the at least one replacement target symbol that was drawn, after the symbol arrangement device arranged at least one of the plurality of symbols. The win determination device is configured to perform a win determination based at least in part on an arrangement of symbols which are in at least a part of the predefined area, after the symbol replacement device replaced, by the at least alternative symbol, the at least one replacement target symbol that was drawn.
US10431030B2
In some embodiments, apparatuses, and methods are provided pertaining to lockers that can be secured in a docking station. In some embodiments, a system comprises a docking station, the docking station configured to selectively secure and release one or more lockers and receive a command to allow one of the one or more lockers to be released, wherein each of the one or more lockers is removable from the docking station, and wherein each of the one or more lockers comprises a storage portion and a securement mechanism for securing each of the one or more lockers to the docking station.