公开(公告)号：EP1178128B1

公开(公告)日：2005-12-14

申请号：EP01202674.6

申请日：2001-07-12

Applicant: Nikko Materials USA, Inc.

Inventor： Wang, Jiangtao ,  Callahan, John ,  Lillie, Dan

IPC: C23C14/02 ,  H05K3/14 ,  C23C28/00 ,  H05K3/16

CPC classification number: C23C2/02 ,  C23C2/26 ,  C23C14/024 ,  C23C14/025 ,  C23C28/044 ,  C23C28/321 ,  C23C28/345 ,  H05K1/167 ,  H05K3/384 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0361 ,  Y10T428/12438 ,  Y10T428/12472

公开(公告)号：EP1550162A4

公开(公告)日：2005-12-07

申请号：EP03754668

申请日：2003-09-15

Applicant: MEDTRONIC MINIMED INC

Inventor： SHAH RAJIV ,  PENDO SHAUN ,  BABIRICKI EDWARD B

IPC: H01L21/48 ,  H05K1/16 ,  H05K3/04 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L2924/0002 ,  H05K1/092 ,  H05K3/4061 ,  H05K3/4647 ,  H05K3/4667 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2203/0278 ,  H01L2924/00

Abstract: A multilayer substrate device formed from a base substrate (12) and alternating metalization layers (14) and dielectric layers (16). Each layer is formed without firing. Vias (44) may extend through one of the dielectric layers (16) such that two metalization layers (14) surrounding the dielectric layers (16) make contact with each other. The vias (44) may be formed by placing pillars (40) on top of a metalization layer (14), forming a dielectric layer (16) on top of the metalization layer (14) and surrounding the pillars (40), and removing the pillars (40). Dielectric layers (16) may be followed by other dielectric layers (16) and metalization layers (14) may be followed by other metalization layers (14).

公开(公告)号：EP1096838A3

公开(公告)日：2005-09-14

申请号：EP00309340.8

申请日：2000-10-24

Applicant: Microcoating Technologies

Inventor： Hunt, Andrew T. ,  Lin, Wen-Yi ,  Carpenter, Richard W.

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/167 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0338 ,  H05K2203/1338 ,  Y10T428/24917

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material (11) and layers of dielectric material (12). Outer resistive material layers (11) are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material (11) on opposite sides of the laminate (10) act as capacitors. Electrical pathways horizontally through resistive material layers (11), which may be connected by via plated holes (14), act as resistors.

Abstract translation: 通过交替沉积，例如通过燃烧化学气相沉积（CCVD），电阻材料层（11）和电介质材料层（12）形成纳米层压材料。 外电阻材料层（11）被图案化以形成电阻材料的离散贴片。 在层叠体（10）的相对侧上的电阻材料（11）的相对的片之间的电通路用作电容器。 可以通过电镀孔（14）连接的可通过电阻材料层（11）水平穿过的电路径用作电阻器。

公开(公告)号：EP1561368A1

公开(公告)日：2005-08-10

申请号：EP03783214.4

申请日：2003-11-07

Applicant: PPG Industries Ohio, Inc.

Inventor： OLSON, Kevin, C. ,  WANG, Alan, E.

IPC: H05K3/44 ,  H01L21/48

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

公开(公告)号：EP1139353A3

公开(公告)日：2004-01-21

申请号：EP01301805.6

申请日：2001-02-28

Applicant: VICTOR COMPANY OF JAPAN, LTD.

Inventor： Shindoh, Motoshi ,  Segawa, Keiji ,  Otsuki, Mitsuru

IPC: H01C1/032 ,  H01C7/00 ,  H01C17/075

CPC classification number: H05K1/167 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board (core material). The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board (core material).

公开(公告)号：EP1093328A3

公开(公告)日：2003-08-13

申请号：EP00308916.6

申请日：2000-10-10

Applicant: ROHM AND HAAS COMPANY

Inventor： Nacker, Wayne E. ,  Carpenter, Richard W.

IPC: H05K3/02 ,  H05K1/16 ,  H01L21/48

CPC classification number: H05K1/167 ,  H01L21/4846 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/027 ,  H05K3/20 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0338

Abstract: To form thin film electrical components, a thin film having desired electrical properties is deposited on a substrate of dissimilar material. Thermal energy from a computer guided laser is used to remove selected portions of the thin film. In accordance with one aspect of the invention, the thin film is an electrically conducting material, such as platinum or doped platinum, and the substrate is metal foil, such as copper foil. The thermal energy from the laser ablates away portions of the thin film. In accordance with another aspect of the invention, a layer of zero valence metal is deposited on a dielectric material substrate which has a melting point or decomposition temperature substantially above that of the zero valence metal. The zero valence metal layer is patterned to form electronic circuitry components by computer guided laser which provides sufficient thermal energy to boil away selected portions of the zero valence metal layer. In one preferred embodiment, electronic circuitry is formed from a three-layer composite comprising nickel foil; a dielectric material, such as silica deposited on the foil; and a zinc layer deposited on the dielectric material. The zinc layer, having a boiling point substantially below the melting points of the dielectric material and the nickel foil, is patterned by laser-derived thermal energy.

公开(公告)号：EP1154480A2

公开(公告)日：2001-11-14

申请号：EP01304076.1

申请日：2001-05-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Mashino, Naohiro

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H01L23/49822 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/053 ,  H05K1/056 ,  H05K1/141 ,  H05K1/162 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09809 ,  H05K2203/0315

Abstract: A multilayer wiring board (101) comprises: a metal substrate (102) as a core, a condenser dielectric layer (102a) formed to cover the metal layer (102) and a condenser electrode metal layer (104) formed to cover the condenser dielectric layer (102a), so that a condenser is defined by the metal substrate (102), the condenser dielectric layer (102a) and the condenser electrode metal layer (104). The condenser dielectric layer (102a) is provided with a first contact hole (102b) to communicate with the metal substrate (102) and the condenser electrode metal layer (104) is provided with a second contact hole (104b) to communicate with the first contact hole, the diameter of the second contact hole (104b) being larger than that of the first contact hole (102b). An insulating layer (111) is formed on the condenser electrode metal layer (104) and is provided with a via hole to communicate with the metal substrate through the second and first contact holes (102b,104b). A metal substrate contact metal layer (112a) is formed on an inner wall of the via hole, so that the metal substrate contact metal layer (112a) comes into electrical contact with the metal substrate (102).

Abstract translation: 多层布线板（101）包括：作为芯的金属基板（102），形成为覆盖金属层（102）的电容器电介质层（102a）和形成为覆盖电容器电介质的电容器电极金属层（104） 层（102a），使得由金属基板（102），电容器介电层（102a）和电容器电极金属层（104）限定冷凝器。 电容电介质层（102a）设置有与金属基板（102）连通的第一接触孔（102b），并且电容器电极金属层（104）设置有与第一接触孔（104b）连通的第二接触孔 接触孔，第二接触孔（104b）的直径大于第一接触孔（102b）的直径。 绝缘层（111）形成在电容器电极金属层（104）上并且设置有通孔，以通过第二和第一接触孔（102b，104b）与金属基板连通。 金属基板接触金属层（112a）形成在通孔的内壁上，金属基板接触金属层（112a）与金属基板（102）电接触。

公开(公告)号：EP1100096A1

公开(公告)日：2001-05-16

申请号：EP00919143.8

申请日：2000-04-19

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： HONDA, Kazuyoshi ,  ECHIGO, Noriyasu ,  ODAGIRI, Masaru ,  SUGIMOTO, Takanori

IPC: H01G4/38

CPC classification number: H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0289 ,  H05K1/141 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/403 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/049 ,  H05K2201/09236 ,  H05K2201/10734

Abstract: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed. An electronic component (10) configured in this manner is mounted on a wiring board, and a semiconductor chip can be mounted thereon. Along with connecting the semiconductor chip to the wiring board via the penetrating electrode (6), the semiconductor chip or the wiring board is connected to the lead electrodes (4, 5). In this manner, while suppressing the size increase of a mounted area, the capacitor or the like can be arranged near the semiconductor chip. Thus, the semiconductor chip is driven with high frequency more easily.

Abstract translation: 电极层（1,2）布置在彼此面对的介电层（3）的两侧，以构成电容器。 在电极层（1,2）中形成引线电极（4,5）。 形成与电极层（1,2）绝缘的穿透电极（6）。 以这种方式配置的电子部件（10）安装在布线板上，并且可以在其上安装半导体芯片。 随着通过穿透电极（6）将半导体芯片连接到布线板，半导体芯片或布线板连接到引线电极（4,5）。 以这种方式，在抑制安装区域的尺寸增加的同时，电容器等可以布置在半导体芯片附近。 因此，更容易地以高频率驱动半导体芯片。

公开(公告)号：EP0899992A3

公开(公告)日：2000-09-06

申请号：EP98306562.4

申请日：1998-08-18

Applicant: LUCENT TECHNOLOGIES INC.

Inventor： Kola, Ratnaji Rao ,  Watts, Roderick Kent ,  Manzione, Louis Thomas

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels (11,23) of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes (12,18) of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects (25).

公开(公告)号：EP1018291A1

公开(公告)日：2000-07-12

申请号：EP98937029.1

申请日：1998-07-20

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： YANG, Rui ,  TRUONG, Thach, G. ,  MOONEY, Justine, A. ,  DAVID, Moses, M.

IPC: H05K3/28 ,  H05K3/38

CPC classification number: H01L23/4985 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0393 ,  H05K3/28 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0323 ,  Y10T428/24917 ,  Y10T428/30 ,  Y10T428/31681 ,  H01L2924/00

Abstract: A flexible circuit carrier (1) including at least one layer of polymer dielectric material (2), at least one layer of conductive material (3) thereover, each layer having two major surfaces, at least one of said layers having at least one aperture therein, wherein at least one layer has a material (4) coated on at least a portion thereof having a Young's Modulus of from 100 to 200 GPa, a dielectric constant (between 45 MHz and 20 GHz) of from 8 to 12, and a Vickers hardness of from 2000 to 9000 kg/mm2 namely diamond-like carbon.