公开(公告)号：EP2004907A2

公开(公告)日：2008-12-24

申请号：EP07727930.5

申请日：2007-04-10

Applicant: Linea Tergi, Ltd.

Inventor： LARSSON, Karl-Gunnar ,  HULT, Anders

IPC: D21H19/02 ,  D21H19/08 ,  C23C26/00 ,  C23C18/16 ,  H05K3/38

CPC classification number: D21H19/02 ,  C23C18/1605 ,  C23C18/1651 ,  C23C18/1692 ,  C23C18/2006 ,  C23C18/2086 ,  C23C18/28 ,  C23C18/31 ,  C23C18/40 ,  C23C26/00 ,  D21H19/08 ,  D21H23/30 ,  H05K1/03 ,  H05K1/032 ,  H05K1/0366 ,  H05K1/038 ,  H05K1/0386 ,  H05K3/181 ,  H05K3/381 ,  H05K2201/0158 ,  H05K2201/0179 ,  H05K2201/0284 ,  H05K2203/095 ,  Y10T428/265 ,  Y10T428/31703

Abstract: There is disclosed a method for applying a first metal on paper, which method comprises the steps a) producing polymers on the surface of said paper, said polymers comprising carboxylic groups and adsorbed ions of at least one second metal, said ions being adsorbed at a pH above 7, b) reducing said ions to the second metal and c) depositing said first metal on the reduced ions of said second metal. The invention further comprises objects manufactured according to the method. Advantages of the present invention include improved adhesion of the metal coating, possibility to coat many difficult materials. The process is suitable for large-scale and continuous production and it will reduce the waste of metal. Circuits manufactured according to the invention display improved signal integrity. Also there is the possibility to manufacture circuits which are built up sequentially with several layers of conductors in distinct patterns. It is also possible to manufacture of circuits with a very small line width.

公开(公告)号：EP1887622A2

公开(公告)日：2008-02-13

申请号：EP07114115.4

申请日：2007-08-09

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Mashino, Naohiro

IPC: H01L23/50

CPC classification number: H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/162 ,  H05K3/007 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/435

Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer (50); a plurality of capacitors (C) arranged side by side in a lateral direction in a state that the capacitors (C) are passed through the base resin layer (50), each of the capacitors (C) constructed by a first electrode (20) provided to pass through the base resin layer (50) and having projection portions (54, 56) projected from both surface sides of the base resin layer (50) respectively such that the projection portion (54) on one surface side of the base resin layer (50) serves as a connection portion (21), a dielectric layer (22) for covering the projection portion (56) of the first electrode (20) on other surface side of the base resin layer (50), and a second electrode (24) for covering the dielectric layer (22); a through electrode (T) provided to pass through the base resin layer (50) and having projection portions (54, 56a) projected from both surface sides of the base resin layer (50) respectively; and a built-up wiring (72, 72a) formed on the other surface side of the base resin layer (50) and connected to the second electrodes (24) of the capacitors (C) and one end side of the through electrode (T).

Abstract translation: 本发明的电容器内置基板包括： 基础树脂层（50）; 在电容器（C）通过基础树脂层（50）的状态下，沿横向并排布置的多个电容器（C），由第一电极（20）构成的每个电容器（C） 被设置为穿过所述基础树脂层（50）并且具有分别从所述基础树脂层（50）的两个表面侧突出的突出部（54,56），使得所述基础树脂的一个表面侧上的突出部（54） 层（50）用作连接部分（21），用于在基底树脂层（50）的另一表面侧覆盖第一电极（20）的突起部分（56）的电介质层（22） 用于覆盖介电层（22）的电极（24）; 设置用于穿过基底树脂层（50）并具有分别从基底树脂层（50）的两个表面侧突出的突出部分（54,56a）的通孔（T） 以及形成在基础树脂层（50）的另一个表面侧并与电容器（C）的第二电极（24）连通并且与通孔电极（T）的一个端部侧连接的积层布线（72,72a） ）。

公开(公告)号：EP1589798A4

公开(公告)日：2007-11-28

申请号：EP03815594

申请日：2003-01-31

Applicant: FUJITSU LTD

Inventor： KOYAMA HIDEKI

IPC: H01L23/498 ,  H01P3/08 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H01L23/12

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01P3/088 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10674

Abstract: A multilayer printed board comprising a plurality of capacitive coupling layers (6) each consisting of a dielectric layer (4) and a power supply layer (3) and a ground layer (5) facing each other while sandwiching the dielectric layer (4), first vias (7) connecting between the power supply layers (3) included in the plurality of capacitive coupling layers (6), and second vias (8) connecting between the ground layers (5) included in the plurality of capacitive coupling layers (6).

公开(公告)号：EP1766672A2

公开(公告)日：2007-03-28

申请号：EP05750364.1

申请日：2005-05-16

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY ,  UNIVERSITY OF SOUTHERN CALIFORNIA

Inventor： RODGER, Damien C. ,  HUMAYUN, Mark ,  TAI, Yu-Chong ,  WEILAND, James D.

IPC: H01L21/50 ,  H01L29/40

CPC classification number: H05K1/032 ,  A61N1/04 ,  A61N1/0543 ,  A61N1/0551 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/007 ,  H05K3/048 ,  H05K3/467 ,  H05K3/4682 ,  H05K2201/0179 ,  H05K2203/016

Abstract: Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched away or otherwise processed to expose the electrodes where stimulation or recording is to occur. All other conductive material in the device is occluded from the environment by the two layers of parylene surrounding it.

公开(公告)号：EP1764810A1

公开(公告)日：2007-03-21

申请号：EP06012013.6

申请日：2006-06-12

Applicant: E.I. Du Pont de Nemours & Company

Inventor： Suh, Seigi ,  Borland, William, J.

IPC: H01G4/12 ,  H05K1/16

CPC classification number: H01L21/02197 ,  H01G4/1227 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31691 ,  H01L28/55 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355

Abstract: The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped with 0.002 - 0.05 atom percent of a dopant comprising an element selected from Sc, Cr, Fe, Co, Ni, Ca, Zn, Al, Ga, Y, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu and mixtures thereof and to capacitors comprising such compositions.

Abstract translation: 本发明涉及一种电介质薄膜组合物，包括：（1）一种或多种钡/选自（a）钛酸钡选择的添加剂，（b）中的任何组合物做了在烧制过程中可以形成的钛酸钡，以及含钛的（c）中 它们的混合物; 溶解于（2）有机介质; 和worin所述薄膜组合物掺杂有0002 - 掺杂剂包括选自Sc，铬，铁，钴，镍，钙，锌，铝，镓，Y，钕，钐，铕，钆选择的元素中的00:05％（原子）， 镝，钬，铒，镱，卢及其混合物和电容器，包括寻求创作。

公开(公告)号：EP1696716A1

公开(公告)日：2006-08-30

申请号：EP04801674.5

申请日：2004-12-06

Applicant: IBIDEN CO., LTD.

Inventor： KARIYA, Takashi ,  MOCHIDA, Akira

IPC: H05K3/46

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷线路板10包括：安装部分60，其上表面上安装有与布线图案32等电连接的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40以及夹持高介电常数层43的第一和第二层电极41和42.第一和第二层电极41和42之一连接到 半导体元件的电源线以及第一和第二层电极41和42中的任一个的另一个连接到地线。 在该多层印刷线路板10中，连接在电源线和接地线之间的层状电容器部分40中包含的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也表现出适当的去耦合效果。

公开(公告)号：EP1550162A2

公开(公告)日：2005-07-06

申请号：EP03754668.6

申请日：2003-09-15

Applicant: Medtronic MiniMed, Inc.

Inventor： SHAH, Rajiv ,  PENDO, Shaun ,  BABIRICKI, Edward, B.

IPC: H01L23/48

CPC classification number: H01L21/4857 ,  H01L2924/0002 ,  H05K1/092 ,  H05K3/4061 ,  H05K3/4647 ,  H05K3/4667 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2203/0278 ,  H01L2924/00

Abstract: A multilayer substrate device formed from a base substrate (12) and alternating metalization layers (14) and dielectric layers (16). Each layer is formed without firing. Vias (44) may extend through one of the dielectric layers (16) such that two metalization layers (14) surrounding the dielectric layers (16) make contact with each other. The vias (44) may be formed by placing pillars (40) on top of a metalization layer (14), forming a dielectric layer (16) on top of the metalization layer (14) and surrounding the pillars (40), and removing the pillars (40). Dielectric layers (16) may be followed by other dielectric layers (16) and metalization layers (14) may be followed by other metalization layers (14).

公开(公告)号：EP1527659A1

公开(公告)日：2005-05-04

申请号：EP03792118.6

申请日：2003-07-03

Applicant: Siemens Aktiengesellschaft

Inventor： BUSCH, Georg

IPC: H05K3/06 ,  H05K1/02

CPC classification number: H05K1/0242 ,  H05K1/0298 ,  H05K1/165 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/061 ,  H05K3/062 ,  H05K2201/0179 ,  H05K2203/107

Abstract: The invention relates to a method for producing electric conductive structures for use in high-frequency technology on a conductive structure carrier at intervals of significantly less than 180 νm, e.g. 30 νm, using microstrip conductors. Said method combines a laser structuring method and an etching method in conjunction with a resist. The resist exhibits characteristics, at least with regard to the laser exposure during the laser structuring method, the etching exposure during the etching method and to its application on the conductive structure carrier in as thin a layer as possible, which at least correspond to those of chemical tin or an amorphic resist

公开(公告)号：EP0899992A2

公开(公告)日：1999-03-03

申请号：EP98306562.4

申请日：1998-08-18

Applicant: LUCENT TECHNOLOGIES INC.

Inventor： Kola, Ratnaji Rao ,  Watts, Roderick Kent ,  Manzione, Louis Thomas

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects.

Abstract translation: 多层印刷电路板的说明书描述和他们在哪电容器和其它无源元件的制造过程被埋入多级电路板之间的水平。 在所述多级结构中的电容器被设计成没有访问被方便地提供以从级间电容板表面或另一板级的平行平板电极连接用通孔互连电镀。

公开(公告)号：EP0497948A1

公开(公告)日：1992-08-12

申请号：EP91914937.0

申请日：1991-08-23

Applicant: THOMSON-CSF

Inventor： LEROY, Michel ,  VAL, Christian

IPC: H01L21 ,  H01L23 ,  H05K3 ,  H05K5

CPC classification number: H05K3/284 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0715 ,  H05K2201/09872 ,  H05K2203/1322

Abstract: Selon un mode de réalisation de l'invention, les composants électroniques discrets ou intégrés, sont encapsulés chacun dans un boîtier, par exemple plastique; les boîtiers sont ensuite montés sur une carte de circuit imprimé, par exemple époxy. L'ensemble composants et carte est recouvert d'une première couche relativement épaisse, constituée par un composé organique et assurant une fonction de nivellement, puis d'une couche telle qu'un composé métallique minéral, ayant pour fonction d'assurer l'herméticité de l'ensemble.