公开(公告)号：EP3220416A1

公开(公告)日：2017-09-20

申请号：EP17163986.7

申请日：2006-01-10

申请人： Micron Technology, Inc.

发明人： TANG, Sanh, D. ,  TUTTLE, Mark E. ,  COOK, Keith R.

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2224/05552

摘要： Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.

摘要翻译： 在焊盘上具有凸点的微电子工件以及制造这种凸点的方法。 例如，这样的工件的一个实施例包括具有多个微电子管芯的衬底，所述多个微电子管芯包括集成电路和电耦合到集成电路的接合焊盘，例如铜接合焊盘。 工件还包括（a）具有多个开口的电介质结构，该多个开口的侧壁从对应的接合焊盘突出，以及（b）多个盖在对应接合焊盘上方。 各个帽可以包括连接到接合垫和开口的侧壁的阻挡层的分立部分，以及阻挡层上的帽层的离散部分。 帽彼此电隔离并且与对应的键合焊盘自对准，而不在帽层上形成掩模层。

公开(公告)号：EP2718964B1

公开(公告)日：2017-08-23

申请号：EP12797279.2

申请日：2012-05-03

申请人： Micron Technology, Inc.

发明人： WOOD, Alan, G. ,  IRELAND, Philip, J.

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03845 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/04941

摘要： Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

摘要翻译： 一些实施例包括形成穿过半导体衬底的互连的方法。 可以形成开口以部分地延伸穿过半导体衬底，并且互连的一部分可以形成在开口内。 另一个开口可以形成为从衬底的第二侧延伸到互连的第一部分，并且互连的另一部分可以形成在该开口内。 一些实施例包括半导体构造，所述半导体构造具有从基板的第一侧部分地穿过半导体基板延伸的贯穿基板互连的第一部分; 并且具有贯穿衬底互连的第二部分，该衬底互连的第二部分从衬底的第二侧延伸并且具有全部延伸到互连的第一部分的多个单独的导电指状物。

公开(公告)号：EP1483789B1

公开(公告)日：2016-11-16

申请号：EP03714137.1

申请日：2003-03-12

申请人： Freescale Semiconductor Inc. (A Delaware Corp)

发明人： DOWNEY, Susan, H. ,  MILLER, James, W. ,  HALL, Geoffrey, B.

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

公开(公告)号：EP2979783A1

公开(公告)日：2016-02-03

申请号：EP14178768.9

申请日：2014-07-28

申请人： Heraeus Deutschland GmbH & Co. KG

发明人： Schäfer, Michael ,  Schmitt, Wolfgang

IPC分类号： B22F5/00 ,  B22F7/04 ,  H05K3/00 ,  H01L23/00

CPC分类号： B22F5/006 ,  B22F7/04 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03505 ,  H01L2224/0351 ,  H01L2224/038 ,  H01L2224/03821 ,  H01L2224/03822 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/05794 ,  H01L2224/058 ,  H01L2224/05839 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/08245 ,  H01L2224/2732 ,  H01L2224/27505 ,  H01L2224/2751 ,  H01L2224/278 ,  H01L2224/27821 ,  H01L2224/27822 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29164 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/80055 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/80395 ,  H01L2224/80439 ,  H01L2224/80447 ,  H01L2224/80464 ,  H01L2224/80487 ,  H01L2224/8084 ,  H01L2224/83055 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83203 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/83447 ,  H01L2224/83464 ,  H01L2224/83487 ,  H01L2224/8384 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/32 ,  H05K2201/10166 ,  H05K2203/0315 ,  H05K2203/0789 ,  H05K2203/1131 ,  H05K2203/1163 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0541 ,  H01L2924/01047

摘要： Verfahren zum Verbinden von Bauelementen, bei dem man eine Anordnung aus wenigstens zwei Bauelementen mit einer aus metallischen Kontaktoberflächen der beiden Bauelemente gebildeten gemeinsamen Kontaktfläche bereitstellt und die Anordnung drucksintert, wobei die metallische Kontaktoberfläche wenigstens eines der beiden Bauelemente mit einer Metalloxidschicht bedeckt ist, und wobei (I) das Drucksintern in einer mindestens eine oxidierbare Verbindung enthaltenden Atmosphäre durchgeführt und/oder (II) die Metalloxidschicht vor Bildung der gemeinsamen Kontaktfläche mit mindestens einer oxidierbaren organischen Verbindung versehen wird.

摘要翻译： 用于连接部件的方法，其中提供至少两种组分的包含两种组分共同接触面的金属接触表面的形成，并且drucksintert的布置，其中，与金属氧化物层中的两种组分的金属接触表面至少覆盖的布置，并且其中（ I）在加压烧结进行至少一种可氧化化合物含有气氛和/或（II）的金属氧化物层之前，形成所述公共的接触面的设置有至少一种可氧化的有机化合物。

公开(公告)号：EP2445000A3

公开(公告)日：2013-06-05

申请号：EP11290473.5

申请日：2011-10-13

申请人： Soitec

发明人： Landru, Didier

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05006 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/04941 ,  H01L2924/00

摘要： The present invention relates to a process for realizing a connecting structure (2200) in a semiconductor substrate (1000), and the semiconductor substrate realized accordingly. The process of the present invention, the semiconductor substrate (1000) having at least a first surface, and being foreseen for a 3D integration with a second substrate (1700) along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value, can include the step of growing a diffusion barrier structure (2211) for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure (2211) being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure (2211) can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure (2211) is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate (1700) is prevented in the integrated state.

公开(公告)号：EP2517239A1

公开(公告)日：2012-10-31

申请号：EP10796036.1

申请日：2010-12-21

申请人： United Monolithic Semiconductors GmbH

发明人： JONSSON, Günter ,  STIEGLAUER, Hermann

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/4827 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05561 ,  H01L2224/05644 ,  H01L2224/291 ,  H01L2224/32221 ,  H01L2224/83101 ,  H01L2224/834 ,  H01L2224/83815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05552

摘要： The invention relates to an electronic component having a GaAs semiconductor substrate (HS), semiconductor components (BE) being implemented on the front side thereof, and the back side thereof having a multilayer backside metallization (RM), wherein an advantageous construction of the layer sequence of the backside metallization is proposed, the backside metallization in particular comprising an Au layer as a bonding layer.

公开(公告)号：EP2240959A1

公开(公告)日：2010-10-20

申请号：EP09700589.6

申请日：2009-01-08

申请人： International Business Machines Corporation

发明人： VOLANT, Richard ,  JONES, Bradley ,  KEI, Ramona ,  WANG, Yun ,  KNAUSS, Raymond ,  COLON, David

IPC分类号： H01L21/4763

CPC分类号： H01L24/03 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014

摘要： An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer to expose the incomplete via opening. Another dielectric layer is formed within the incomplete via opening to compensated for differences in the total dielectric thickness above the metal line relative to an optimal dielectric stack. A photoresist is applied thereupon and patterned. An anisotropic etch process for formation of a normal via opening may be employed with no or minimal modification to form a proper via opening and to expose the metal line. A metal pad is formed upon the metal line so that electrical contact is provided between the metal pad and the metal line.

公开(公告)号：EP1399966A2

公开(公告)日：2004-03-24

申请号：EP02744379.5

申请日：2002-06-17

申请人： Infineon Technologies AG

发明人： FRIESE, Gerald

IPC分类号： H01L23/58 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/04941

摘要： A structure for a bond pad used on a semiconductor device, in accordance with the present invention, includes a metal layer, an interconnect formed through a dielectric layer connecting to the metal layer and a bond pad having a first portion disposed over the metal layer and the interconnect, and a second portion disposed over the dielectric layer. The first portion includes a bond area for providing an attachment point for a connection, and the second portion includes a probe area for providing contact with a probe.

摘要翻译： 根据本发明的用于半导体器件的键合焊盘的结构包括金属层，通过连接到金属层的电介质层形成的互连和具有设置在金属层上的第一部分的键合焊盘和 互连件以及设置在介电层上的第二部分。 第一部分包括用于提供用于连接的附接点的结合区域，并且第二部分包括用于提供与探针接触的探针区域。

公开(公告)号：EP0825646B1

公开(公告)日：2003-05-02

申请号：EP97114374.8

申请日：1997-08-20

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Anand, Minakshisundaran Balasubramanian

IPC分类号： H01L23/485 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/45124 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48766 ,  H01L2224/85201 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2224/05556 ,  H01L2924/00

公开(公告)号：EP0973198A3

公开(公告)日：2003-03-19

申请号：EP99202296.2

申请日：1999-07-14

申请人： Texas Instruments Incorporated

发明人： Saran, Mukul

IPC分类号： H01L23/485

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01013 ,  H01L2924/00 ,  H01L2224/05552

摘要： An architecture and method of fabrication for an integrated circuit having a reinforced bond pad comprising at least one portion of the integrated circuit disposed under the bond pad; and this at least one circuit portion comprises at least one dielectric layer and a patterned electrically conductive reinforcing structure disposed in this at least one dielectric layer.

摘要翻译： 一种用于具有加强接合焊盘的集成电路的结构和制造方法，所述加固接合焊盘包括设置在接合焊盘下方的集成电路的至少一部分; 并且该至少一个电路部分包括设置在该至少一个电介质层中的至少一个电介质层和图案化的导电加强结构。