公开(公告)号：EP2454752B1

公开(公告)日：2015-09-09

申请号：EP10734619.9

申请日：2010-07-14

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： NYGAARD, Paul A. ,  MOLIN, Stuart B. ,  STUBER, Michael A.

IPC分类号： H01L21/78 ,  H01L23/36 ,  H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/786 ,  H01L23/367

CPC分类号： H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/45099

摘要： Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

公开(公告)号：EP2937898A1

公开(公告)日：2015-10-28

申请号：EP15171021.7

申请日：2010-07-14

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Nygaard, Paul A. ,  Molin, Stuart B. ,  Stuber, Michael A.

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/786 ,  H01L21/78 ,  H01L23/36

CPC分类号： H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/45099

摘要： Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

摘要翻译： 本发明的实施例提供了绝缘体上半导体（SOI）结构的散热。 在一个实施例中，公开了一种用于制造集成电路的方法。 在第一步中，在SOI晶片的有源层中形成有源电路。 在第二步骤中，从设置在SOI晶片的背面的衬底层去除衬底材料。 在第三步骤中，绝缘体材料从SOI晶片的背面去除以形成挖掘的绝缘体区域。 在第四步骤中，在所述挖掘的绝缘体区域上沉积散热层。 散热层是导热和电绝缘的。

公开(公告)号：EP2847796A1

公开(公告)日：2015-03-18

申请号：EP13721698.2

申请日：2013-05-06

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： HUET, Stéphanie ,  AIT-MANI, Abdenacer ,  DI CIOCCIO, Léa

IPC分类号： H01L27/146

CPC分类号： H01L27/1469 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1465 ,  H01L27/14687 ,  H01L27/14692 ,  H01L2224/03845 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/19 ,  H01L2224/221 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12043 ,  H01L2924/351 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： The invention relates to a method for producing at least one photosensitive infrared detector by assembling a first electronic component (100, 230) comprising a plurality of photodiodes (110) sensitive to infrared radiation and a second electronic component (400) comprising at least one electronic circuit for reading the plurality of photodiodes, the method being characterised in that it comprises: the production, on each of the first (100, 230) and second (400) components, of a connection surface (192, 492) formed at least partially by a layer (210, 405) containing silicon oxide (SiO2); and a step of adhering the first component (100, 230) and the second component (400) by means of the connection surfaces (192, 492) thereof, enabling the direct adhesion the two components (100, 230, 400). This method enables the simplification of the hybridisation of heterogeneous components for the production of an infrared detector. The invention also relates to an infrared detector and to an assembly for producing such a detector.

摘要翻译： 一种用于通过组装包括对红外线辐射敏感的多个光电二极管的第一电子部件和包括至少一个用于读取多个光电二极管的电子电路的第二电子部件来生产至少一个光敏红外检测器的方法，红外检测器和用于产生 这种检测器，该方法包括：在第一和第二部件中的每一个上，至少部分地由基于氧化硅（SiO 2）的层形成的连接面; 通过其连接面接合第一部件和第二部件，从而执行两个部件的直接接合。 该方法可以简化用于产生红外检测器的异质组分的杂交。

公开(公告)号：EP3111467A2

公开(公告)日：2017-01-04

申请号：EP15706806.5

申请日：2015-02-26

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： GONDCHARTON, Paul ,  BENAISSA, Lamine ,  IMBERT, Bruno ,  MORICEAU, Hubert

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/485

CPC分类号： H01L24/83 ,  H01L21/185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/2745 ,  H01L2224/2755 ,  H01L2224/27845 ,  H01L2224/29147 ,  H01L2224/80055 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8092 ,  H01L2224/80948 ,  H01L2224/83895 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01008 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/00012

摘要： Process for producing a structure by direct adhesive bonding of two elements comprising the production of the elements to be assembled and the assembly of said elements, in which the production of the elements to be assembled comprises the steps: - deposition on a substrate of a TiN layer by physical vapour deposition, - deposition of a copper layer on the TiN layer, and in which the assembly of said elements comprises the steps: - polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, - bringing said surfaces into contact, - storing said structure at atmospheric pressure and at ambient temperature.

摘要翻译： 待组装和元件的组装生产的元件的：一种用于通过两个元件，所述方法包括直接键合制造结构的方法。 生产的元件的组装，包括：在TiN层上的铜层的通过物理气相沉积TiN层，和沉积的底物沉积。 的元件的组件包括：抛光预期会接触，从而thatthey具有小于1个纳米RMS和亲水性能的粗糙度铜层的表面，使表面接触，并在大气压下和在存放结构 环境温度。

公开(公告)号：EP2826061A1

公开(公告)日：2015-01-21

申请号：EP13760569.7

申请日：2013-02-12

申请人： Micron Technology, Inc.

发明人： GANDHI, Jaspreet, S.

IPC分类号： H01L21/28 ,  H01L21/304

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

公开(公告)号：EP2718964B1

公开(公告)日：2017-08-23

申请号：EP12797279.2

申请日：2012-05-03

申请人： Micron Technology, Inc.

发明人： WOOD, Alan, G. ,  IRELAND, Philip, J.

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03845 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/04941

摘要： Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

摘要翻译： 一些实施例包括形成穿过半导体衬底的互连的方法。 可以形成开口以部分地延伸穿过半导体衬底，并且互连的一部分可以形成在开口内。 另一个开口可以形成为从衬底的第二侧延伸到互连的第一部分，并且互连的另一部分可以形成在该开口内。 一些实施例包括半导体构造，所述半导体构造具有从基板的第一侧部分地穿过半导体基板延伸的贯穿基板互连的第一部分; 并且具有贯穿衬底互连的第二部分，该衬底互连的第二部分从衬底的第二侧延伸并且具有全部延伸到互连的第一部分的多个单独的导电指状物。

公开(公告)号：EP3024019A1

公开(公告)日：2016-05-25

申请号：EP14194506.3

申请日：2014-11-24

申请人： IMEC VZW

发明人： KIM, Soon-Wook ,  Peng, Lan ,  Verdonck, Patrick ,  Miller, Robert ,  Beyer, Gerald ,  Beyne, Eric

IPC分类号： H01L21/60 ,  H01L23/31

CPC分类号： H01L24/83 ,  H01L21/02065 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03845 ,  H01L2224/03848 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/32501 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/83031 ,  H01L2224/83047 ,  H01L2224/83048 ,  H01L2224/83359 ,  H01L2924/00012 ,  H01L2924/0504 ,  H01L2924/00014 ,  H01L2924/20106 ,  H01L2924/2011

摘要： The present invention is related to a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding, wherein the substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Preferably, the dielectric layer after CMP has an roughness of less than 0.2nm RMS. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometre. Preferably the RMS value after CMP is less than 0.1nm. Then the substrates are subjected to a pre-bond annealing step. The substrates are then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250°C, preferably between 200°C and 250°C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

摘要翻译： 本发明涉及通过直接接合将第一半导体衬底接合到第二半导体衬底的方法，其中衬底都在其与电介质层的接触表面上设置，随后是用于降低电介质粗糙度的CMP步骤 层。 优选地，CMP之后的介电层具有小于0.2nm RMS的粗糙度。 然后在电介质层上沉积一层SiCN，接着进行CMP步骤，将SiCN层的粗糙度降低到十分之一纳米。 CMP后的RMS值优选小于0.1nm。 然后对基板进行预结合退火步骤。 然后通过直接接合将基底粘合，可能之前是接触表面的一个或多个预处理，然后在小于或等于250℃，优选在200℃之间的后结合退火步骤 C和250℃。 已经发现，即使在上述命名的退火温度下，粘结强度也是优异的，其比现有技术中已知的低。

公开(公告)号：EP2454752A1

公开(公告)日：2012-05-23

申请号：EP10734619.9

申请日：2010-07-14

申请人： Io Semiconductor

发明人： NYGAARD, Paul A. ,  MOLIN, Stuart B. ,  STUBER, Michael A.

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/45099

摘要： Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

公开(公告)号：EP2826061A4

公开(公告)日：2016-03-16

申请号：EP13760569

申请日：2013-02-12

申请人： MICRON TECHNOLOGY INC

发明人： GANDHI JASPREET S

IPC分类号： H01L21/768 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

公开(公告)号：EP2718964A4

公开(公告)日：2014-11-26

申请号：EP12797279

申请日：2012-05-03

申请人： MICRON TECHNOLOGY INC

发明人： WOOD ALAN G ,  IRELAND PHILIP J

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03845 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/04941

摘要： Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

摘要翻译： 一些实施例包括形成穿过半导体衬底的互连的方法。 的开口可以形成穿过半导体衬底延伸中途，以及互连的一部分可以在该开口内形成。 另一个开口可以形成为从基板的第二侧延伸到互连的第一部分，以及互连的另一部分可以搜索开口内形成。 一些实施例包括具有通过从所述基板的第一侧上的半导体衬底部分地延伸贯穿互连衬底的第一部分半导体构造; 并具有从所述基板的第二侧延伸的贯穿互连衬底的第二部分和具有多个单独的导电指状物所做的一切延伸到互连件的第一部分。