公开(公告)号：EP2848100A1

公开(公告)日：2015-03-18

申请号：EP12770294.2

申请日：2012-05-07

Applicant: Johnson Controls Automotive Electronics SAS

Inventor： BARILLER, Jean-Marie ,  VAN LIERE, Keith ,  KOEPP, Thomas

IPC: H05K1/02 ,  G01R31/28 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40

CPC classification number: G01R31/2818 ,  G01R31/2812 ,  H05K1/0268 ,  H05K1/116 ,  H05K3/3484 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/0367 ,  H05K2201/099

Abstract: The present invention relates to a printed circuit board (1) comprising at. least one board with a printed circuit and a via (5) and a probe access structure (8), which is in electrical contact with the via (5), wherein one end region (10) of the via (5) is provided with a conductive layer (7) which is in electrical contact with the probe access structure (8).

公开(公告)号：EP2621250B1

公开(公告)日：2014-02-26

申请号：EP13152505.7

申请日：2013-01-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Muramatsu, Shigetsugu ,  Shimizu, Hiroshi ,  Horikawa, Yasuyoshi

IPC: H05K1/02 ,  H05K1/05 ,  F21K99/00 ,  H05K3/34

CPC classification number: H05K7/2039 ,  F21K9/90 ,  F21V7/00 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/056 ,  H05K3/3452 ,  H05K3/46 ,  H05K2201/0191 ,  H05K2201/09409 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054

公开(公告)号：EP2621249A1

公开(公告)日：2013-07-31

申请号：EP13152287.2

申请日：2013-01-23

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Nakanishi, Tsukasa ,  Nakamura, Atsushi ,  Matsumoto, Takayuki

IPC: H05K1/02 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0201 ,  H01L25/0753 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/113 ,  H05K3/00 ,  H05K3/0061 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2924/00014

Abstract: A printed wiring board includes an insulative substrate (110), a wiring portion (130A-E) which is formed on a surface of the insulative substrate and has a predetermined wiring pattern, an insulative layer (150) which is formed on the wiring portion and on which a part of the wiring layer is exposed as a terminal (160A, 160B), a radiator plate (180) provided on another surface of the insulative substrate, and a heat conductive portion (140) which is formed inside the through hole penetrating through the surface and the other surface of the insulative substrate and connected to the wiring portion.

Abstract translation: 印刷线路板包括绝缘基板（110），形成在绝缘基板的表面上并具有预定布线图案的布线部（130A-E），形成在布线部上的绝缘层（150） 并且其上布线层的一部分作为端子暴露于其上，设置在绝缘基板的另一表面上的散热板（180）和形成在该通孔内的导热部分（140） 穿过绝缘衬底的表面和另一表面并连接到布线部分。

公开(公告)号：EP1740029B1

公开(公告)日：2012-09-12

申请号：EP06012641.4

申请日：2006-06-20

Applicant: OMRON Automotive Electronics Co., Ltd.

Inventor： Higasa, Koichi, c/o Omron Corporation ,  Sumimoto, Yoshiyuki, c/o Omron Corporation ,  Yoshioka, Daisuke, c/o Omron Corporation

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3452 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/341 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2201/2036 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

公开(公告)号：EP1796445A3

公开(公告)日：2011-09-14

申请号：EP07002566.3

申请日：1997-06-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H01L23/498 ,  H01L23/538

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprising a core substrate, multilayer wiring layers formed on the substrate by alternately laminating an interlaminar insulating layer and conductor pattern and a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers, characterized in that first, the solder pads located from first row to fifth row from an outer position of the solder pad group are constructed with flat pads connected to conductor patterns located on the outermost surface and having solder bumps formed on surfaces of the pads, while the solder pad group other than these solder pads are constructed with viaholes connected to a flat innerlayer pad group located in an inner layer and having solder bumps formed in recess portions of the viaholes and, second, the solder pads located from first row to fifth row from an outer position of the innerlayer pad group are constructed with flat pads connected to conductor patterns in the same layer as the innerlayer pad group, while the innerlayer pad group other than these pads are constituted with flat pads connected to a further innerlayer flat pad group located inward the above innerlayer through viaholes and, third, the layer having the structure of the above second feature is at least one layer.

公开(公告)号：EP0907308B1

公开(公告)日：2011-01-26

申请号：EP97924262.5

申请日：1997-05-28

Applicant: ROHM CO., LTD.

Inventor： NAKAMURA, Satoshi

IPC: H05K3/34

CPC classification number: H05K3/3405 ,  H05K1/111 ,  H05K3/0097 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3484 ,  H05K3/403 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/1028 ,  H05K2201/1034 ,  H05K2203/0545 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: A method for mounting terminal on circuit board includes an applying process for applying solder paste (3) to a desired circuit board (1), a laying process for laying the connecting ends (4a) of terminals (4) having the connecting ends (4a) and non-connecting ends (4b) on the parts coated with the paste (3), and a heating process for melting the paste (3) for soldering the connecting ends (4a) to the board (1). In the applying process, a plurality of sets of solder paste applying parts (3a-3d) which are separated from each other are provided on the board (1). In the laying process, each connecting end (4a) is laid across each set of parts (3a-3d).

公开(公告)号：EP2161976A1

公开(公告)日：2010-03-10

申请号：EP07721472.4

申请日：2007-06-15

Applicant: Princo Corp.

Inventor： YANG, Chih-kuang ,  HSING, Chieh-Lin

IPC: H05K3/34

CPC classification number: H05K3/4007 ,  H05K3/107 ,  H05K3/20 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099

Abstract: A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.

Abstract translation: 多层基板的表面处理结构及其制造方法。 本发明的表面光洁度结构包括接合焊盘层，至少一个覆盖金属层和焊接掩模。 覆盖金属层覆盖接合焊盘层。 焊接掩模具有用于暴露覆盖金属层的孔。 本发明可以形成覆盖金属层以覆盖接合焊盘层，然后形成焊接掩模。 此后，在覆盖金属层的位置处将该孔制成焊料掩模以使其露出。 由于接合焊盘层嵌入在多层基板的电介质层中，所以可以提高接合焊盘层与电介质层之间的粘合强度。 同时，可以通过覆盖金属层来防止接合焊盘层与焊料的接触。

公开(公告)号：EP2134147A2

公开(公告)日：2009-12-16

申请号：EP09161821.5

申请日：2009-06-03

Applicant: Valeo Equipements Electriques Moteur

Inventor： Mandion, Thierry ,  Chemin, Michaël

IPC: H05K3/34

CPC classification number: H05K3/3421 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K1/111 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/09918 ,  H05K2201/10166 ,  H05K2203/166 ,  Y02P70/613 ,  H01L2924/00

Abstract: L'invention concerne un procédé de positionnement d'un circuit intégré (3) du type dit à montage en surface, notamment du type "D 2 PAK-7", et de soudure sur un substrat à plages métallisées isolées (50 à 52). Typiquement les plages métallisées isolées sont en cuivre et ont une épaisseur supérieure ou égale à 50 microns. La distance séparant (L 7 ) les plages métallisées sous-jacentes aux broches de grille (31) et de première source (32) étant critique, cette distance est rendue égale à celle séparant les deux broches (31, 32). Pour pouvoir opérer un positionnement et un alignement optiques des broches (31 à 33, 35 à 37) par rapport aux plages métallisées (50 à 52), on dépose entre les paires de broches des bandes (40 à 43) de vernis isolant formant repères d'index.

Abstract translation: 该方法包括在沉积铜段（50，51）的基片，即上表面上 检查绝缘金属基板（IMS）中，由预定的区域做了铜段（50）的宽度等于一个连接销（31）的宽度。 绝缘清漆条带（40）在由铜部分的相对的边缘限定的区域上沉积。 连接销和另一销连接（32）的相对的边缘被定位和对使用频带通过以索引标记在光学方法中的铜部分的相对边缘对齐。 销被焊接在铜的部分。 因此独立claimsoft被包括在组件用于组装的表面安装上的基片类型的集成电路。

公开(公告)号：EP1968360A1

公开(公告)日：2008-09-10

申请号：EP07103774.1

申请日：2007-03-08

Applicant: IEE INTERNATIONAL ELECTRONICS & ENGINEERING S.A.

Inventor： Maoujoud, Mohammed

IPC: H05K1/02

CPC classification number: H05K1/0281 ,  H05K1/0271 ,  H05K1/118 ,  H05K3/28 ,  H05K2201/0133 ,  H05K2201/09881 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/2009

Abstract: Method for manufacturing a flexible printed circuit (10) is disclosed, wherein a conductor circuit pattern (12) is formed on a flexible dielectric substrate (14). The flexible printed circuit is reinforced by applying lines and/or shapes of flexible dielectric material (16) over the substrate (14) at predetermined locations so that they are located between the elements (12) of the circuit pattern, the flexible dielectric material (16) having a greater elasticity than that of said circuit pattern (12).

Abstract translation: 公开了一种用于制造柔性印刷电路（10）的方法，其中导体电路图案（12）形成在柔性电介质基片（14）上。 柔性印刷电路通过在预定位置在衬底（14）上施加柔性电介质材料（16）的线和/或形状来加强，使得它们位于电路图案的元件（12）之间，柔性电介质材料 16）具有比所述电路图案（12）更大的弹性。

公开(公告)号：EP1824911B1

公开(公告)日：2008-08-13

申请号：EP05854264.8

申请日：2005-12-14

Applicant: EASTMAN CHEMICAL COMPANY

Inventor： PECORINI, Thomas, Joseph ,  MCWILLIAMS, Douglas, Stephens ,  GILLIAM, Spencer, Allen ,  TINCHER, Mark, Elliott ,  TANNER, Candace, Michele

IPC: C08J5/18

CPC classification number: H05K1/0326 ,  C08J5/18 ,  C08J2367/02 ,  H05K1/0393 ,  H05K1/116 ,  H05K3/281 ,  H05K3/386 ,  H05K3/429 ,  H05K2201/0145 ,  H05K2201/0969 ,  H05K2201/099 ,  Y10T428/1086 ,  Y10T428/2852 ,  Y10T428/31504 ,  Y10T428/31507 ,  Y10T428/31786

Abstract: Disclosed is a biaxially-oriented polyester film produced from a polyester comprising: (1) diacid residues comprising between about 95 and about 100 mole percent of terephthalic acid residues; (2) diol residues comprising between about 95 and about 100 mole percent of 1,4-­cyclohexanedimethanol residues; and (3) about 0.5 to about 5 mole percent of another dicarboxylic acid or diol residue, wherein the polyester comprises a total of 100 mole percent diacid residues and a total of 100 mole percent diol residues. In one embodiment, the biaxially-oriented film has a thickness of 70 to 150 microns (3-5 mils). In another embodiment, the biaxially-oriented film undergoes not more than 3% shrinkage when immersed for 10 seconds in a solder bath preheated to 260°C. The film can be made by stretching an essentially amorphous cast-film of thickness between about 450-1800 micron (18-70 mil) at a ratio from about 2.5x2.5 to 3.5x3.5 while being held at a temperature between 90°C and 130°C, and heat-setting the stretched film at an actual film temperature of from 260°C to Tm, where Tm is the melting point of the polyester as measured by differential scanning calorimetry (DSC), while maintaining the dimensions of the stretched film.