公开(公告)号：EP2582218B1

公开(公告)日：2017-06-07

申请号：EP12188067.8

申请日：2012-10-11

Applicant: Funai Electric Co., Ltd.

Inventor： Yokawa, Akira ,  Kita, Yuki ,  Fujikawa, Akihiro ,  Fukumoto, Yasuyuki ,  Mori, Yasuhiro ,  Suzuki, Yuto ,  Horiuchi, Hirofumi ,  Tsuji, Hirohiko ,  Yamanaka, Takahito ,  Yonezawa, Hideo

IPC: H05K7/20 ,  G02B6/00 ,  H05K1/02 ,  G02F1/13357 ,  G02F1/1333 ,  G06F1/16

CPC classification number: G02B6/0088 ,  G02B6/0068 ,  G02B6/0073 ,  G02B6/0085 ,  G02F1/133615 ,  G02F2001/133314 ,  G02F2001/133317 ,  G02F2001/133328 ,  G02F2001/133628 ,  G06F1/20 ,  H05K1/0209 ,  H05K7/20963 ,  H05K2201/0162 ,  H05K2201/09909

Abstract: This display (100) includes a light source portion (6a, 6b, 6c), a first heat radiation member (10) for radiating heat generated by the light source portion, a rear housing (4) covering the first heat radiation member in a state in contact with the first heat radiation member, and a cover member (5) covering a rear surface of the rear housing so that the rear surface of the rear housing is partially exposed outward. The first heat radiation member is arranged on a region corresponding to a region of the rear housing exposed outward from the cover member as viewed from the side of the rear surface.

Abstract translation: 该显示器100包括光源部6a，6b，6c，用于散发由光源部产生的热量的第一散热构件10，以及覆盖第一散热构件的后壳体4， 与第一散热构件接触的状态;以及盖构件（5），其覆盖后壳体的后表面，使得后壳体的后表面部分地向外暴露。 从背面侧观察，第一散热部件配置在与从罩部件向外侧露出的后壳体的区域对应的区域。

公开(公告)号：EP2738798A1

公开(公告)日：2014-06-04

申请号：EP12817380.4

申请日：2012-07-20

Applicant: Kyocera Corporation

Inventor： TSUJINO, Mahiro ,  MIYAHARA, Manabu

IPC: H01L23/04

CPC classification number: H01L24/42 ,  H01L23/057 ,  H01L23/10 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/171 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/09909 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device housing package(1) includes a base body (5) having, on its upper surface, a mounting region for placement of a semiconductor device (3); a frame body (7) having a frame-like portion disposed on the upper surface of the base body (5) so as to surround the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member (9) disposed in the opening so as to extend from an interior of the frame body (7) to an exterior thereof; wiring conductors (11) disposed on an upper surface of the insulating member (9) so as to extend from the interior of the frame body (7) to the exterior thereof; and a continuous metallic film (35) disposed on a part of the upper surface of the insulating member (9), the metallic film (35) lying outside the frame body (7) so as to surround the wiring conductors (11).

公开(公告)号：EP2731410A1

公开(公告)日：2014-05-14

申请号：EP13179698.9

申请日：2013-08-08

Applicant: Nitto Denko Corporation

Inventor： Masuda, Shotaro ,  Baba, Toshikazu ,  Ishimaru, Yasuto

IPC: H05K1/02

CPC classification number: G02B6/12002 ,  G02B6/138 ,  H05K1/0274 ,  H05K1/028 ,  H05K2201/09236 ,  H05K2201/09909 ,  H05K2201/09972 ,  H05K2203/1572

Abstract: An opto-electric hybrid board which is capable of significantly reducing stresses applied to a bent portion thereof is provided. The opto-electric hybrid board includes a stacked electric circuit board (E) and an optical waveguide (W). The electric circuit board (E) includes an insulative layer (1) having front and back surfaces, electrical interconnect lines (2) formed on the front surface of the insulative layer (1), and an insulative coverlay (3) formed on the front surface of the insulative layer (1) and for covering and protecting the electrical interconnect lines (2). The optical waveguide (W) includes a first cladding layer (6) having a front surface, cores (7) formed in a pattern on the front surface of the first cladding layer (6), and a second cladding layer (8) covering the cores (7). Part of the opto-electric hybrid board is defined as a to-be-bent portion inwhich the coverlay (3) and the optical waveguide (W) are disposed in non-overlapping relation.

Abstract translation: 提供能够显着降低施加到其弯曲部分的应力的光电混合板。 光电混合基板包括堆叠电路板（E）和光波导（W）。 电路板（E）包括具有前表面和后表面的绝缘层（1），形成在绝缘层（1）的前表面上的电互连线（2）和形成在绝缘层（1）上的绝缘覆盖层 绝缘层（1）的表面并且用于覆盖和保护电互连线（2）。 光波导（W）包括具有前表面的第一包层（6），在第一包层（6）的前表面上以图案形成的芯体（7）和覆盖第一包层 核心（7）。 光电混合板的一部分被定义为覆盖层（3）和光波导（W）以非重叠关系设置的弯曲部分。

公开(公告)号：EP2717338A1

公开(公告)日：2014-04-09

申请号：EP12792316.7

申请日：2012-03-22

Applicant: Sharp Kabushiki Kaisha

Inventor： HATA, Toshio ,  AGATANI, Makoto ,  UEMURA, Toyonori ,  ISHIZAKI, Shinya ,  MATSUSHITA, Hitoshi

IPC: H01L33/50 ,  F21S2/00 ,  H01L33/52 ,  F21Y101/02

CPC classification number: F21V3/02 ,  F21K9/232 ,  F21K9/235 ,  F21K9/237 ,  F21K9/60 ,  F21K9/64 ,  F21K9/68 ,  F21V3/00 ,  F21V23/001 ,  F21V29/77 ,  F21Y2101/00 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/508 ,  H01L2224/48137 ,  H01L2924/3025 ,  H05B33/0845 ,  H05B33/0857 ,  H05B37/0272 ,  H05K1/0274 ,  H05K1/11 ,  H05K3/28 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2203/049 ,  H01L2924/00

Abstract: The light-emitting device (100) includes a substrate (101) and a plurality of light-emitting sections. A first light-emitting section is made up of LED chips (102) and a first fluorescent-substance-containing resin layer (107), and a second light-emitting section is made up of LED chips (102) and a second fluorescent-substance-containing resin layer (108). The first fluorescent-substance-containing resin layer (107) and the second fluorescent-substance-containing resin layer (108) are provided in a plurality of locations such that the fluorescent-substance-containing resin layers for the different light-emitting sections are adjacently arranged.

公开(公告)号：EP2173147A1

公开(公告)日：2010-04-07

申请号：EP07790805.1

申请日：2007-07-13

Applicant: Ibiden Co., Ltd.

Inventor： TAKAHASHI, Michimasa ,  AOYAMA, Masakazu

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/0366 ,  H05K3/0035 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/091 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/09909 ,  H05K2203/1536

Abstract: A wiring board 19 is structured by laminating first substrate 1, second substrate 2 having a smaller mounting area than that of first substrate 1, and base substrate 3 positioned between first substrate 1 and second substrate 2, where at least a portion of the periphery is made thinner than the central portion. Vias 44 are formed in at least either first substrate 1 or second substrate 2. In base substrate 3, the thickness of the portion bonded only to first substrate 1 is less than that of the portion sandwiched between first substrate 1 and second substrate 2.

Abstract translation: 布线板19通过层叠第一基板1，安装面积小于第一基板1的第二基板2和位于第一基板1和第二基板2之间的基板3而构成，其中至少一部分周边是 比中央部分薄。 在第一基板1或第二基板2中的至少一个中形成通路44.在基板3中，仅与第一基板1接合的部分的厚度小于夹在第一基板1与第二基板2之间的部分的厚度。

公开(公告)号：EP2044819A1

公开(公告)日：2009-04-08

申请号：EP07729103.7

申请日：2007-05-14

Applicant: Continental Automotive GmbH

Inventor： FISCHER, Georg ,  LOIBL, Josef ,  SMIRRA, Karl

IPC: H05K3/28 ,  H05K3/00

CPC classification number: H05K3/28 ,  H05K1/118 ,  H05K1/141 ,  H05K1/142 ,  H05K1/147 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2203/1147 ,  Y10T29/49155 ,  Y10T29/49158

Abstract: In order to produce a first flexible conductor carrier (2A), at least one conductor track (6) is applied to a base insulating film (4). Furthermore, a covering layer is applied to the conductor track (6) and the base insulating film (4) in such a way that, in at least one conduction region (8) of the first flexible conductor carrier (2A), the conductor track (6) is completely enclosed by the covering layer and the base insulating film (4). In at least one insulating region (9), the base insulating film (4) is free of the conductor track (6) and the covering layer. In at least one contact region (7) of the first flexible conductor carrier (2A) the conductor track (6) is free of the covering layer.

公开(公告)号：EP1744605A3

公开(公告)日：2008-06-11

申请号：EP06014276.7

申请日：2006-07-10

Applicant: Seiko Epson Corporation

Inventor： Hashimoto, Nobuaki

IPC: H05K1/16

CPC classification number: H01L23/3114 ,  G02F1/13452 ,  H01L23/5228 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01066 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/167 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09909 ,  H05K2203/0361 ,  H01L2924/00 ,  H01L2924/01028

Abstract: An electronic board includes: a substrate (P); and a wiring pattern (20, 21) provided on the substrate (P) and having a part that forms a resistance element (R), the part having wiring specifications that are different from those of other parts.

公开(公告)号：EP1871153A2

公开(公告)日：2007-12-26

申请号：EP07011995.3

申请日：2007-06-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Muramatsu, Shigetsugu ,  Kobayashi, Tsuyoshi ,  Kurihara, Takshi

IPC: H05K3/40 ,  H05K3/32 ,  H01L23/498

CPC classification number: H05K3/4647 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/48227 ,  H05K1/111 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y02P70/611

Abstract: In a semiconductor apparatus, a semiconductor element (70,71) is mounted on a wiring substrate (31). Wiring patterns (40) and protrusions (32) are formed on a surface of a substrate (30) with the wiring patterns (40) extending on tops of the protrusions (32). The surface of the substrate (30) on which the wiring patterns (40) are formed are covered with an insulating layer (60). Surfaces of connection parts (40c) of the wiring patterns (40) formed on the tops of the protrusions (32) are formed with the surfaces of the connection parts (40c) exposed to a surface of the insulating layer (60) on a level with the surface of the insulating layer (60) or in a position lower than the surface of the insulating layer. The connection parts (40c) are formed as pads for connection formed in alignment with connection electrodes of the semiconductor element. The semiconductor element (70,71) is mounted by making electrical connection to the connection parts (40c) by flip chip bonding.

Abstract translation: 在半导体装置中，将半导体元件（70,71）安装在布线基板（31）上。 布线图案（40）在突起（32）的顶部延伸，形成在基板（30）的表面上的布线图案（40）和突起（32）。 其上形成有布线图案（40）的基板（30）的表面被绝缘层（60）覆盖。 形成在突起（32）的顶部上的布线图案（40）的连接部分（40c）的表面形成有暴露于绝缘层（60）的表面的连接部分（40c）的表面在一定程度上 与绝缘层（60）的表面或位于比绝缘层的表面低的位置。 连接部分（40c）形成为与半导体元件的连接电极对准的连接用焊盘。 半导体元件（70,71）通过倒装芯片接合与连接部件（40c）进行电连接来安装。

公开(公告)号：EP1814370A1

公开(公告)日：2007-08-01

申请号：EP05811438.0

申请日：2005-12-02

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： WATANABE, Masaki, Matsushita Eletric Industrial Co., Ltd.

IPC: H05K3/34 ,  H01L21/60 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/3452 ,  H01L2224/16225 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/429 ,  H05K2201/09036 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10734 ,  H05K2203/0588 ,  Y10T29/49144

Abstract: The invention provides a printed circuit board capable of mounting BGA or other IC package of narrow terminal interval by using through-holes of conventional size. On one principal surface of printed circuit board (1), soldering lands (2a), (2b), (2c), and (2d) for connecting solder balls are disposed in lattice. Central point (B) of through-hole (3) is set eccentric to the side of soldering land (2a) at the same potential as through-hole (3), remote from intersection (A) formed by diagonal line (200ab) linking soldering lands (2a) and (2b) and diagonal line (200cd) linking soldering lands (2c) and (2d).

Abstract translation: 本发明通过使用通孔常规尺寸提供了一种能够安装BGA或窄终端间隔的其它IC封装的印刷电路板。 在印刷电路板（1），焊料焊接区（2A），（2B），（2c）和（2d）的用于连接的焊料球的一个主表面被布置在晶格内。 中心点的贯通孔（3）被设定偏心焊国家（2a）的侧面处于相同的电位为通孔（3）中，远离交点（A）而形成由对角线（200AB）的（B）的连接 焊料焊接区（2a）和（2b）和对角线（200CD）连接的焊料焊接区（2c）和（2d）的。

公开(公告)号：EP1779421A1

公开(公告)日：2007-05-02

申请号：EP05778204.7

申请日：2005-08-01

Applicant: Hitek Power Corporation

Inventor： WING, Kenneth, E. ,  CARROLL, Scott, T.

IPC: H01L21/56

CPC classification number: H05K3/305 ,  H01L21/56 ,  H01L2924/0002 ,  H05K3/284 ,  H05K2201/0187 ,  H05K2201/09909 ,  H05K2203/0126 ,  H05K2203/1476 ,  Y02P70/613 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2924/00

Abstract: A method for the selective encapsulation (14) of electronic components (10) on a printed circuit board (12) comprising, in one embodiment, the steps of delivering the printed circuit board to an encapsulating nest at room temperature; damming the target areas with a dam resin having a latent curing agent and deposited in the shape of walls of predetermined heights, according to the desired fill heights; dispensing a fill resin to fill the dammed areas; and curing the dam and fill resins for a suitable amount of time. In a different embodiment, the invention comprises the additional steps of laying resin beads (20), each in a position corresponding to the footprint of each target component (22); and of positioning the target components over the beads and soldering the components.