公开(公告)号：EP0989789B1

公开(公告)日：2007-03-21

申请号：EP99307407.9

申请日：1999-09-17

Applicant: NEC-Mitsubishi Electric Visual Systems Corporation

Inventor： Nojioka, Shinichi

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3452 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10651 ,  Y10S428/901 ,  Y10T428/24281 ,  Y10T428/24802

公开(公告)号：EP1043922B1

公开(公告)日：2007-02-14

申请号：EP98961576.0

申请日：1998-12-24

Applicant: IBIDEN CO., LTD.

Inventor： SHIRAI, Seiji, Ogaki-kita-kojou, Ibiden K. K. ,  SHIMADA, Kenichi, Ogaki-kita-kojou, Ibiden K. K. ,  ASAI, Motoo, Ogaki-kita-kojou, Ibiden K. K.

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K1/113 ,  H05K1/115 ,  H05K3/184 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/384 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/099

Abstract: A multilayer printed wiring board having a field via structure and having an excellent connection reliability between via holes. A lower-layer via hole (50) having a flat surface is formed by filling up an opening (42) provided in a lower interlayer resin insulating layer (40) with a plating metal (48), and an upper-layer via hole (70) is formed by providing an opening (62) in an upper interlayer resin insulating layer (60) of the via hole (50). Since the lower-layer via hole (50) has a flat surface and no resin is left on the surface, the connection reliability between the via hole (50) and the upper-layer via hole (70) is secured. In addition, since the surface of the via hole (50) is flat, the surface smoothness of the multilayer printed wiring board is not marred even when the upper-layer via hole (70) is formed on the via hole (50).

Abstract translation: 一种具有场过孔结构并且在通孔之间具有优异的连接可靠性的多层印刷线路板。 通过用电镀金属（48）填充设置在下层层间树脂绝缘层（40）中的开口（42）形成具有平坦表面的下层通孔（50），并且形成上层通孔 70）通过在通孔（50）的上部层间树脂绝缘层（60）中提供开口（62）而形成。 由于下层通孔（50）具有平坦表面并且表面上没有树脂，因此确保了通孔（50）与上层通孔（70）之间的连接可靠性。 另外，由于通孔（50）的表面是平坦的，所以即使在通孔（50）上形成上层通路孔（70），也不会损害多层印刷布线板的表面平滑度。

公开(公告)号：EP1602265A2

公开(公告)日：2005-12-07

申请号：EP04717495.8

申请日：2004-03-04

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： VANDER PLAS, Hubert, A. ,  BERAUER, Frank

IPC: H05K3/34

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10157 ,  H05K3/3452 ,  H05K3/403 ,  H05K2201/09154 ,  H05K2201/099 ,  H05K2203/0568 ,  H05K2203/1394 ,  H01L2224/0401

Abstract: A method for depositing a solder layer (280) or solder bump on a sloped surface (220). The method includes etching a sloped surface on a planar semiconductor substrate (200), depositing a solder-wettable layer (230) on the sloped surface, masking the wettabler layer with a coating layer (240) to control the position of the solder deposition, and using an organic film (250) to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.

公开(公告)号：EP1337134A3

公开(公告)日：2005-05-04

申请号：EP03250776.6

申请日：2003-02-07

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Hirose, Yoshitaka, c/o Alps Electric Co., Ltd.

IPC: H05K1/11 ,  H05K3/34 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L2224/16 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2203/041 ,  Y02P70/611

Abstract: The present invention intends to provide a terminal structure strong in the peel strength of a land portion and a ball. In a terminal structure according to the invention, a land portion (2) includes a terminal portion for soldering a ball (7) ; a support portion (4) disposed in the neighborhood of an outer periphery portion of the terminal portion; and a link portion (5) for linking the terminal portion and the support portion; and wherein on a base material, with an entirety of the terminal portion including an edge portion located in the outer periphery portion of the terminal portion exposed, an insulating layer (6) is disposed so as to cover the support portion; and with a solder straddled a surface and an edge portion of the terminal portion, the ball is soldered to the terminal portion. Accordingly, the terminal structure that is large in the peel strength of the ball from the terminal portion and of the terminal portion from the base material can be obtained.

公开(公告)号：EP1043922A4

公开(公告)日：2004-06-23

申请号：EP98961576

申请日：1998-12-24

Applicant: IBIDEN CO LTD

Inventor： SHIRAI SEIJI ,  SHIMADA KENICHI ,  ASAI MOTOO

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/34 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4644 ,  H05K1/113 ,  H05K1/115 ,  H05K3/184 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/384 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/099

Abstract: A multilayer printed wiring board having a field via structure and having an excellent connection reliability between via holes. A lower-layer via hole (50) having a flat surface is formed by filling up an opening (42) provided in a lower interlayer resin insulating layer (40) with a plating metal (48), and an upper-layer via hole (70) is formed by providing an opening (62) in an upper interlayer resin insulating layer (60) of the via hole (50). Since the lower-layer via hole (50) has a flat surface and no resin is left on the surface, the connection reliability between the via hole (50) and the upper-layer via hole (70) is secured. In addition, since the surface of the via hole (50) is flat, the surface smoothness of the multilayer printed wiring board is not marred even when the upper-layer via hole (70) is formed on the via hole (50).

Abstract translation: 一种具有场过孔结构并且在通孔之间具有优异的连接可靠性的多层印刷线路板。 通过用电镀金属（48）填充设置在下层层间树脂绝缘层（40）中的开口（42）形成具有平坦表面的下层通孔（50），并且形成上层通孔 70）通过在通孔（50）的上部层间树脂绝缘层（60）中提供开口（62）而形成。 由于下层通孔（50）具有平坦表面并且表面上没有树脂，因此确保了通孔（50）与上层通孔（70）之间的连接可靠性。 另外，由于通孔（50）的表面是平坦的，所以即使在通孔（50）上形成上层通路孔（70），也不会损害多层印刷布线板的表面平滑度。

公开(公告)号：EP1313143A2

公开(公告)日：2003-05-21

申请号：EP02025833.1

申请日：2002-11-18

Applicant: GENNUM CORPORATION

Inventor： The designation of the inventor has not yet been filed

IPC: H01L23/498 ,  H01L23/538

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K2201/09481 ,  H05K2201/099 ,  H01L2924/00

Abstract: A thick film circuit with a perimeter anchored thick film pad is provided. The thick film circuit includes a base substrate, a thick film bonding pad, and a solder mask layer. The thick film bonding pad is formed on the surface of the base substrate. The solder mask layer is also formed on the surface of the base substrate, and overlaps a portion of the thick film bonding pad in order to improve adhesion between the thick film bonding pad and the base substrate.

Abstract translation: 提供了具有周边锚定厚膜垫的厚膜电路。 厚膜电路包括基底基板，厚膜接合焊盘和焊接掩模层。 在基底基板的表面上形成厚膜接合焊盘。 焊接掩模层也形成在基底衬底的表面上，并与厚膜接合焊盘的一部分重叠，以便改善厚膜焊盘和基底衬底之间的密合性。

公开(公告)号：EP0957520A3

公开(公告)日：2001-10-31

申请号：EP99302924.8

申请日：1999-04-15

Applicant: SONY CORPORATION

Inventor： Oya, Yoichi

IPC: H01L23/498 ,  H05K3/30 ,  H05K3/34

CPC classification number: H01L24/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress. To ensure the joint strength based on a conductive material layer and enhance the mount reliability by making fine the terminals on a relay substrate which correspond to the input or output terminals of a semiconductor chip, and making the pitch narrow.

Abstract translation: 半导体封装P1的封装侧焊盘3a完全暴露在阻焊层5的开口5a中。安装板B1的板侧焊盘12a也完全暴露在阻焊层13的开口13a中 当半导体封装件P1和安装板B1通过焊接层14a彼此接合时，焊接层14a与焊盘3a和12a接触，同时延伸到其侧壁表面，使得焊接层14a的接合强度 可以通过增加的接触面积和形状来增强。 当焊盘3a和12a的尺寸和形状被设定为彼此相等时，焊接层14a被成形为具有大致均匀截面的柱，从而防止局部应力集中。 为了确保基于导电材料层的接合强度，并且通过使对应于半导体芯片的输入或输出端子的继电器基板上的端子精细化并使间距变窄，增强了安装可靠性。

公开(公告)号：EP0709883B1

公开(公告)日：2001-10-04

申请号：EP95111618.5

申请日：1995-07-24

Applicant: NEC CORPORATION

Inventor： Urushima, Michitaka, c/o NEC Corporation

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L24/50 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49572 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H05K1/0269 ,  H05K1/111 ,  H05K3/3452 ,  H05K3/363 ,  H05K2201/0108 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/099 ,  H05K2201/10681 ,  H05K2201/10734 ,  Y02P70/611

公开(公告)号：EP0814643A3

公开(公告)日：1999-04-14

申请号：EP97109609.4

申请日：1997-06-12

Applicant: IBIDEN CO, LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H01L23/498

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprises a core substrate, multilayer wiring layers formed on the substrate by alternately laminating an interlaminar insulating layer and conductor circuit, and a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers, in which the solder pads located from first row to fifth row from an outer position of the solder pad group are constructed with flat pads connected to conductor pattern located on the outermost surface and solder bumps formed on the surfaces of the pads, while the solder pad group other than these solder pads are constructed with viaholes connected to flat innerlayer pad group located in an inner layer and solder bumps formed in recess portions of the viaholes, and the solder pads located from first row to fifth row from an outer position of the innerlayer pad group are constructed with flat pads connected to conductor patterns in the same layer as the innerlayer pad group, while the innerlayer pad groups other than the pads are constituted with flat pads connected to a further innerlayer flat pad group located inward the above innerlayer through viaholes.

公开(公告)号：EP0521982B1

公开(公告)日：1996-07-17

申请号：EP91906887.4

申请日：1991-03-21

Applicant: FERGUSON LIMITED

Inventor： ROWE, John Michael

IPC: H05K3/34

CPC classification number: H05K1/116 ,  H05K3/0094 ,  H05K3/3452 ,  H05K3/3468 ,  H05K2201/09663 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2203/044

Abstract: To prevent that holes (3) of a circuit board not equipped with circuit elements and designed for later equipment are filled by soldering material (5), a small solder resisting strip (6) is printed upon the conductor (2) diametrically transversing said hole (3).