公开(公告)号：EP0242962A1

公开(公告)日：1987-10-28

申请号：EP87302007.7

申请日：1987-03-09

申请人： INMOS CORPORATION

发明人： Wilson, David S. ,  Kiffe, Dennis O.

IPC分类号： H01L23/48

CPC分类号： H01L23/49503 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45014 ,  H01L2224/45099 ,  H01L2224/4516 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/01028 ,  H01L2924/013 ,  H01L2924/01404 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead frame for the manufacture of semiconductor devices having an offset die pad (57) positioned closer to a first carrier strip (59) of the lead frame than to a second carrier strip (61) of the lead frame. Die (42), such as memory chips, which are designed for end-only wire bonding, may be centred on the off-centre die pads. This enables bonding wires (50) to be used which are all substantially equal in length. Having the die centred also increases the efficiency of manufacture of semiconductor devices and increases the reliability of each semiconductor device.

摘要翻译： 一种用于制造半导体器件的引线框架，其具有位于比引线框架的第二载体带（61）更靠近引线框架的第一载体条（59）的偏移管芯焊盘（57）。 设计用于仅针对引线键合的诸如存储器芯片的芯片（42）可以在离心芯片焊盘上居中。 这使得能够使用长度都基本相等的接合线（50）。 使模具居中的同时也提高了半导体器件的制造效率，并增加了每个半导体器件的可靠性。

公开(公告)号：EP0228869A3

公开(公告)日：1987-09-16

申请号：EP86309867

申请日：1986-12-17

申请人： AMERICAN TELEPHONE AND TELEGRAPH COMPANY

发明人： Moyer, Harold William ,  Scholz, Harry Robert

IPC分类号： H01L23/48

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/09701 ,  H01L2924/1815 ,  Y10T29/49121 ,  H01L2924/00014

摘要： Disclosed is a semiconductor package with a high pin count. External contacts to the chip are provided by interdigitated leads (l3, l4 - l6, l7) formed from an upper (l5) and lower (l2) lead frame. The lower lead frame includes a paddle (ll) for mounting the chip (l0). The upper lead frame initially has its leads tied together (30-33) and a center portion is punched out to fit the size of the particular chip. The two lead frames are preferably coplanar in the area around the boundaries of the package encapsulant.

公开(公告)号：EP0142938A1

公开(公告)日：1985-05-29

申请号：EP84307060.8

申请日：1984-10-16

申请人： AT&T Corp.

发明人： Graver, Ronald Norman

IPC分类号： H01L23/48 ,  H01L23/50

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49589 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/12033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In an integrated circuit package, the central "paddle" of the lead frame on which the semiconductor chip (17) is mounted comprises two separate, electrically isolated portions (10, 11) which extend beyond edges of the chip and which is each electrically connected to a different terminal pin of the package. External power is applied to these two chip support portions by means of which electrical power can be distributed to numerous areas (as desired) on the chip via bonding wires (23, 24) extending between the chip areas and the paddle portions.

摘要翻译： 提出使用专门设计的引线框架分配断电芯片的新方式。 引线框架的支撑板电分割并且提供至少两个导体构件，其布置成在芯片接合到桨之后在芯片下方交叉。 功率和/或接地可以通过在横梁的末端或附近提供接合位置而分布到芯片的两个或更多个边缘。 芯片本身与十字接头元件电隔离。

公开(公告)号：EP0078606A3

公开(公告)日：1985-04-24

申请号：EP82305087

申请日：1982-09-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Orcutt, John W.

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00011 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599

摘要： An assembly having an integral wire support (110) located between the contact pads (92, 97) of a semiconductor device (22) and a lead frame (20) for supporting wires (102) attached between the contact pads (97) of the semiconductor device (22) and the contact pads (47) of the lead frame (20).

摘要翻译： 一种具有位于半导体器件（22）的接触焊盘（92,97）之间的整体电线支架（110）的组件和用于支撑电线（102）的引线框架（20），所述引线框架（102）附接在所述接触焊盘 半导体器件（22）和引线框架（20）的接触焊盘（47）。

公开(公告)号：EP0063408A1

公开(公告)日：1982-10-27

申请号：EP82301300.8

申请日：1982-03-15

申请人： AMP INCORPORATED (a New Jersey corporation)

发明人： Grabbe, Dimitry G.

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L23/49503 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

摘要： A ceramic chip carrier having a copper lead frame (3) bonded directly to a ceramic substrate (1) has a common rim (13, 23) connecting the tip portions (7) of the leads. The rim (13,23) is raised above the substrate (1) and does not bond to the substrate (1) and is removed after bonding. In one embodiment the rim (13) is of reduced thickness to space it from the substrate (1) and a perforated ground pad (10) may be provided which is connected to the rim (13) by tabs (14). In another embodiment the rim (23) is provided with extended portions (15) which permit bending the rim (23) away from the substrate without altering the relative positions of the tip portions (7).

摘要翻译： 具有直接接合在陶瓷基板（1）上的铜引线框架（3）的陶瓷芯片载体具有共同的边缘（13,23）。连接引线的末端部分（7）。 边缘（13,23）在衬底（1）上方升高，并且不结合到衬底（1）并且在结合之后被去除。 在一个实施例中，边缘（13）具有减小的厚度以将其从衬底（1）放置，并且可以提供穿孔接地垫（10），其通过接片（14）连接到轮辋（13）。 在另一个实施例中，边缘（23）设置有延伸部分（15），其允许边缘（23）远离基底弯曲，而不改变尖端部分（7）的相对位置。

公开(公告)号：EP2622653B1

公开(公告)日：2018-12-05

申请号：EP11832905.1

申请日：2011-07-20

申请人： SunPower Corporation

发明人： LINDERMAN, Ryan ,  JOHNSTON, Keith ,  PHU, Thomas ,  DAWSON, Matthew

IPC分类号： H01L33/62

CPC分类号： H01L31/05 ,  H01L23/49503 ,  H01L31/024 ,  H01L31/044 ,  H01L31/048 ,  H01L31/0504 ,  H01L31/0508 ,  H01L31/0516 ,  H01L31/052 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： Interconnects for optoelectronic devices are described. An interconnect may include a stress relief feature. An interconnect may include an L-shaped feature.

公开(公告)号：EP3101685A4

公开(公告)日：2018-03-14

申请号：EP14824341

申请日：2014-01-29

申请人： RENESAS ELECTRONICS CORP

发明人： IGRARASHI TAKAYUKI ,  FUMAYA TAKUO

IPC分类号： H01L21/822 ,  H01L23/00 ,  H01L23/495 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04 ,  H01L27/06 ,  H01L27/12

CPC分类号： H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

摘要： Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4 > DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil; CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

公开(公告)号：EP3264457A1

公开(公告)日：2018-01-03

申请号：EP17170726.8

申请日：2017-05-11

申请人： NXP USA, Inc.

发明人： FOONG, Chee Seng

IPC分类号： H01L23/495 ,  H01L23/31

CPC分类号： H01L23/49555 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49551 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. Leads in a first subset of the leads alternate with leads in a second subset of the leads. The inner portion of the first subset of the leads is bent. The die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads are encapsulated. A second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material.

摘要翻译： 一种制造封装集成电路器件的方法包括形成引线框架，引线框架具有内部部分和外部部分，引线的内部部分位于管芯焊盘的外围之间并且延伸至管芯周围的开口的一端 垫。 引线的外部部分沿其长度几乎直到开口的相对端。 导线的第一个子集中的导线与导线的第二个子集中的导线交替排列。 引线的第一子集的内部是弯曲的。 芯片焊盘，引线的内部以及仅与引线的内部相邻的开口的第一部分被封装。 开口的第二部分和引线的输出部分形成封装材料的挡条。

公开(公告)号：EP3108503A4

公开(公告)日：2017-11-22

申请号：EP15751635

申请日：2015-02-20

申请人： TEXAS INSTRUMENTS INC

发明人： JOSHI RAJEEV DINKAR

IPC分类号： H01L23/495 ,  H01L23/498

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/49861 ,  H01L25/165 ,  H01L25/50 ,  H02M7/003

摘要： Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

公开(公告)号：EP3213344A1

公开(公告)日：2017-09-06

申请号：EP15766449.1

申请日：2015-09-16

申请人： Conti Temic microelectronic GmbH

发明人： POLA, Olivier ,  WALK, Michael

IPC分类号： H01L23/495 ,  H01L23/492 ,  H01L25/07

CPC分类号： H01L23/562 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/0603 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/41113 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014

摘要： Disclosed is a leadframe (AR) for a semiconductor component (HB), comprising: - a recess (AS); - an electrically conducting terminal element (PF), located in the recess (AS), for establishing an electrical connection to the semiconductor component (HB); - an isolating element (IS) that is located in the recess (AS), mechanically connects the terminal element (PF) to the leadframe (AR), and electrically isolates the terminal element (PF) from the leadframe (AR).

摘要翻译： 公开了一种用于半导体组件（HB）的引线框架（AR），包括： - 凹部（AS）;以及 - - 位于所述凹部（AS）中的用于建立到所述半导体部件（HB）的电连接的导电端子元件（PF）; - 位于凹槽（AS）中的隔离元件（IS），将端子元件（PF）机械连接到引线框架（AR），并且将端子元件（PF）与引线框架（AR）电隔离。