公开(公告)号：EP3158839A1

公开(公告)日：2017-04-26

申请号：EP15812624.3

申请日：2015-06-23

申请人： Zglue, Inc.

发明人： NASRULLAH, Jawad ,  ZHANG, Ming

IPC分类号： H05K7/14 ,  H05K1/14

CPC分类号： H01L22/34 ,  G06F17/5077 ,  H01L22/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81908 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

摘要翻译： 一种系统gemäß到在一些实施例中包括一个基片，其可包括附连槽的多个用于附连到其上。 一个或多个附连槽的可以是可编程的附连槽。 基底芯片还可以包括电路，其用于互连以便附接到基座芯片。 对于实施例，基底芯片可以包括横杆交换机的复数，每个的所有其与附接槽的多个respectivement者相关联。 基底芯片还可以包括一个配置块，所有这些是angepasst接收和发送一个或多个附连槽的确定性采矿电连接的信号线的测试信号。当一个或多个这些被连接到基座芯片和所有其进一步angepasst接收配置 用于编程信号（包括电源和地）横杆交换机的信道的数据。

公开(公告)号：EP2482311A3

公开(公告)日：2016-06-08

申请号：EP12150102.7

申请日：2012-01-03

申请人： Fujitsu Limited

发明人： Akamatsu, Toshiya

IPC分类号： H01L23/498 ,  H01L21/98 ,  H01L25/065 ,  H01L23/14 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11002 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16141 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83102 ,  H01L2224/9201 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15159 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/18 ,  H05K1/181 ,  H05K2201/09063 ,  H05K2201/1053 ,  H05K2201/10545 ,  H05K2201/10674 ,  H01L2224/13099 ,  H01L2224/11 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/48624 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor element (2) and an electronic element (3). The semiconductor element has a first protruding electrode (2a), and the electronic element has a second protruding electrode (3a). A substrate (4) is disposed between the semiconductor element (2) and the electronic element (3). The substrate has a through-hole (4a) in which the first and second protruding electrodes (2a, 3a) are fitted. The first and second protruding electrodes are connected together inside the through-hole (4a) of the substrate.

公开(公告)号：EP2482311A2

公开(公告)日：2012-08-01

申请号：EP12150102.7

申请日：2012-01-03

申请人： Fujitsu Limited

发明人： Akamatsu, Toshiya

IPC分类号： H01L23/498 ,  H01L21/98 ,  H01L25/065 ,  H01L23/14 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11002 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16141 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83102 ,  H01L2224/9201 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15159 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/18 ,  H05K1/181 ,  H05K2201/09063 ,  H05K2201/1053 ,  H05K2201/10545 ,  H05K2201/10674 ,  H01L2224/13099 ,  H01L2224/11 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/48624 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor element (2) and an electronic element (3). The semiconductor element has a first protruding electrode (2a), and the electronic element has a second protruding electrode (3a). A substrate (4) is disposed between the semiconductor element (2) and the electronic element (3). The substrate has a through-hole (4a) in which the first and second protruding electrodes (2a, 3a) are fitted. The first and second protruding electrodes are connected together inside the through-hole (4a) of the substrate.

摘要翻译： 一种半导体器件，包括：半导体元件（2）和电子元件（3）。 该半导体元件具有第一突出电极（2a）中，所述电子元件具有第二突出电极（3a）的。 A底（4）的半导体元件（2）和（3）电子元件之间设置。 基板具有其中第一和第二突出电极（2A，3A）嵌合的通孔（4a）中。 第一和第二突出电极连接在一起的内部通孔（4a）的基板。

公开(公告)号：EP2260508A1

公开(公告)日：2010-12-15

申请号：EP09731239.1

申请日：2009-04-07

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： DI CIOCCIO, Léa ,  GROSSI, François ,  GUEGUEN, Pierric ,  VANDROUX, Laurent

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L21/98

CPC分类号： H01L24/83 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/90 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/80004 ,  H01L2224/80143 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83002 ,  H01L2224/83141 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/95085 ,  H01L2224/95146 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/0665 ,  H01L2924/00

摘要： The invention relates to a method of forming, on the surface of a substrate (2), at least one hydrophilic attachment zone (12) for the purpose of self-assembling a component or a chip (3), in which a hydrophobic zone (20), which delimits said hydrophilic attachment zone, is produced.

公开(公告)号：EP2206145A2

公开(公告)日：2010-07-14

申请号：EP08835829.6

申请日：2008-09-26

申请人： Tessera, Inc.

发明人： KWON, Jinsu

IPC分类号： H01L21/60

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/2064 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099

摘要： A packaged microelectronic assembly includes a microelectronic element (104) having a front surface (122) and a plurality of first solid metal posts (110) extending away from the front surface (122). Each of the first posts (110) has a width in a direction of the front surface (122) and a height extending from the front surface (122), wherein the height (H2) is at least half of the width (Wl). There is also a substrate (102) having a top surface (101) and a plurality of second solid metal posts (108) extending from the top surface (102) and joined to the first solid metal posts (110).

公开(公告)号：EP2054933A4

公开(公告)日：2010-04-21

申请号：EP07764102

申请日：2007-07-23

申请人： INTELLECTUAL VENTURES FUND 27

发明人： KOK CHI WAH ,  TAM YEE CHING

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/142 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/09427 ,  H05K2201/09472 ,  H05K2201/09509 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor package structure for flip chip package includes at least a patterned circuit layer and an insulating layer alternately stacking up each other. The patterned layer includes a plurality of bump pads, and the insulating layer includes a plurality of etching holes. The etching holes and the bump pads are aligned, such that the bump pads are exposed through the etching holes. A plurality of bumps is disposed on the active surface of the chip, which can be obtained by stud bumping. The etching holes are filled with solder paste, and the bumps of the chips penetrate into the solder filled etching holes. Vibration obtained by mechanical equipment, or ultrasonic equipment can be applied to assist the alignment of the bumps to the corresponding bump pads. A reflow process is applied to collapse the solder paste that fills the etching holes to form electrical connection between the bumps and bump pads.

公开(公告)号：EP2093791A2

公开(公告)日：2009-08-26

申请号：EP09007758.7

申请日：2002-02-25

申请人： Chippac, Inc.

发明人： Pendse, Rajendra ,  Ahmad, Nazir ,  Chen, Andrea ,  Kim, Kyung-Moon ,  Kweon, Young Do ,  Tam, Samuel

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099

摘要： A flip chip package is formed by a solid-state bond technique for connecting the input/ouput pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board. According to the aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

摘要翻译： 通过固态键合技术形成倒装芯片封装，用于连接集成电路芯片上的输入/输出焊盘和封装衬底。 固态键合技术涉及金属表面的直接配合，并且不使用任何颗粒状导电材料。 因此，与ACA或ICA微粒互连相比，连接能够承载非常高的电流，并且显示良好的长期可靠性。 此外，固态键合技术不需要任何互连材料的熔化或流动。 因此，连接可以以非常精细的几何形状形成，通常低至70微米间距。 此外，集成电路芯片的表面和封装衬底的下表面之间的空间填充有图案化的粘合剂结构，其由一个或多个粘合材料组成，所述粘合剂材料以指定的图案相对于 封装和印刷电路板之间的第二级互连。 根据本发明的方面，可以调整覆盖在第二级连接区域上的封装结构的热膨胀系数和符合性，以减少在封装上的第二级连接中产生的应力的潜在的破坏性传播到 集成电路芯片，从而延长封装和互连的长期可靠性。

公开(公告)号：EP2054933A1

公开(公告)日：2009-05-06

申请号：EP07764102.5

申请日：2007-07-23

申请人： Intellectual Ventures Fund 27 LLC

发明人： KOK, Chi Wah ,  TAM, Yee Ching

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/60 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/142 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/09427 ,  H05K2201/09472 ,  H05K2201/09509 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor package structure for flip chip package includes at least a patterned circuit layer and an insulating layer alternately stacking up each other. The patterned layer includes a plurality of bump pads, and the insulating layer includes a plurality of etching holes. The etching holes and the bump pads are aligned, such that the bump pads are exposed through the etching holes. A plurality of bumps is disposed on the active surface of the chip, which can be obtained by stud bumping. The etching holes are filled with solder paste, and the bumps of the chips penetrate into the solder filled etching holes. Vibration obtained by mechanical equipment, or ultrasonic equipment can be applied to assist the alignment of the bumps to the corresponding bump pads. A reflow process is applied to collapse the solder paste that fills the etching holes to form electrical connection between the bumps and bump pads.

公开(公告)号：EP1378932B1

公开(公告)日：2007-04-04

申请号：EP03014236.8

申请日：2003-06-25

申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.

发明人： Murayama, Kei

IPC分类号： H01L21/00

CPC分类号： H01L24/81 ,  H01L23/544 ,  H01L24/75 ,  H01L2223/54473 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75743 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor chip mounting apparatus able to raise the positional accuracy when mounting a semiconductor chip on a package including a stage on which the substrate is carried, a visible light source for directly illuminating the substrate from above the stage, a semiconductor chip conveying means for holding from one surface the semiconductor chip comprised of silicon formed to a thickness through which visible light can pass and conveying it on the substrate carried on the stage, a capturing means arranged at a position facing the stage and capturing visible light passing through the semiconductor chip held by the semiconductor chip conveying means so as to capture patterns formed on the substrate carried on the stage and the semiconductor chip, and a positioning means for positioning the semiconductor chip on the substrate based on the patterns of the substrate and the semiconductor chip captured by the capturing means.

公开(公告)号：EP0890989A4

公开(公告)日：2006-11-02

申请号：EP98900725

申请日：1998-01-22

申请人： ROHM CO LTD

发明人： HIKITA JUNICHI ,  SHIBATA KAZUTAKA ,  YAMAGUCHI TSUNEMORI ,  MORIFUJI TADAHIRO ,  MIYATA OSAMU

IPC分类号： G01P3/488 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/544 ,  G01P3/488 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2224/05554 ,  H01L2224/1147 ,  H01L2224/13016 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/29455 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/78281 ,  H01L2224/78301 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83136 ,  H01L2224/8319 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83907 ,  H01L2224/85181 ,  H01L2224/90 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first and a second semiconductor chip (14, 16). On the surface of the first semiconductor chip (14), a plurality of first electrodes are formed. On the surface of the second semiconductor chip (16), a plurality of second electrodes are formed. By placing the first and the second semiconductor chip (14, 16) so that their surfaces may face each other, the first electrodes and the second electrodes are connected to each other. On the surface of each of the semiconductor chips (14, 16), circuit elements are also formed and these circuit elements mounted on the first and the second semiconductor chip (14, 16) are covered by the second and the first semiconductor chip (16, 14) respectively. The connections of the first and the second semiconductor chip (14, 16) are sealed in a package (26) by synthetic resin which has an excellent moistureproof property, and the entire bodies of the first and the second semiconductor chip (14, 16) are airtightly sealed in a package (22) by the second synthetic resin.

摘要翻译： 半导体器件包括第一和第二半导体芯片。 第一半导体芯片在其表面上形成有多个第一电极，而第二半导体芯片在其表面上形成有多个第二电极。 这些表面被定位成彼此面对，由此连接在第一电极和第二电极之间。 各个表面形成有电路元件。 电路元件由第一半导体芯片和第二半导体芯片覆盖。其连接部分处的第一半导体芯片和第二半导体芯片由耐湿性优异的合成树脂封装。 第一半导体芯片和第二半导体芯片由粘合性优异的第二合成树脂整体封装。