公开(公告)号：JP5497815B2

公开(公告)日：2014-05-21

申请号：JP2012034812

申请日：2012-02-21

Applicant: ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： 芳高 佐々木 ,  浩幸 伊藤 ,  寛 池島 ,  淳 飯島

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

公开(公告)号：JP2013026615A

公开(公告)日：2013-02-04

申请号：JP2012051467

申请日：2012-03-08

Applicant: Headway Technologies Inc ,  ヘッドウェイテクノロジーズ インコーポレイテッド ,  Sae Magnetics(H K )Ltd ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： SASAKI YOSHITAKA ,  ITO HIROYUKI ,  IKEJIMA HIROSHI ,  IIJIMA ATSUSHI

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/27 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To easily achieve a package at low cost, the package having a function equal to that of a package that does not include a semiconductor chip which does not operate normally even when including a semiconductor chip which does not operate normally.SOLUTION: A composite layered chip package 1 includes a plurality of subpackages 1A-1E. Each of the subpackages includes a body and wiring. The body has a main part including a plurality of layer portions 10, and a first terminal and a second terminal arranged on the upper surface and the lower surface of the main part, respectively. The wiring is connected to the first and second terminals. In all of the subpackages, the number of the layer portions 10 is equal, and the plurality of layered portions 10 include at least one first type layer portion. In at least two of the plurality of subpackages, the plurality of layer portions 10 further include a second type layer portion. A semiconductor chip of the first type layer portion is connected to the wiring, and a semiconductor chip of the second type layer portion is not connected to the wiring.

Abstract translation: 要解决的问题为了容易地以低成本实现封装，封装具有与不包括半导体芯片的功能相同的功能，即使在包括不工作的半导体芯片的情况下也不能正常工作 一般。 复合分层芯片封装1包括多个子封装1A-1E。 每个子包包括一个主体和接线。 主体具有包括多个层部分10的主要部分和分别布置在主要部分的上表面和下表面上的第一端子和第二端子。 接线连接到第一和第二端子。 在所有子部件中，层部10的数量相等，多个分层部10至少包括一个第一类型的层部。 在多个子包中的至少两个子包中，多层层10还包括第二类型层部分。 第一型层部分的半导体芯片连接到布线，并且第二类型层部分的半导体芯片没有连接到布线。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012256845A

公开(公告)日：2012-12-27

申请号：JP2012034812

申请日：2012-02-21

Applicant: Headway Technologies Inc ,  ヘッドウェイテクノロジーズ インコーポレイテッド ,  Sae Magnetics(H K )Ltd ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： SASAKI YOSHITAKA ,  ITO HIROYUKI ,  IKEJIMA HIROSHI ,  IIJIMA ATSUSHI

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To achieve a laminated chip package at low cost, which allows a plurality of laminated chip packages to be laminated and electrically connected with each other.SOLUTION: A laminated chip package 1 comprises: a body 2; and wiring 3. The body 2 includes more than two layered parts 10 and has a main part 2M having a tip face and an undersurface, a plurality of first terminals 4 arranged on the top face of the main part 2M, and a plurality of second terminals arranged on the undersurface of the main part 2M. The layered part 10 includes a semiconductor chip having a first surface and a second surface, and a plurality of electrodes provided on the first surface side and connected to the wiring 3. A first layered part nearest to the top face of the main part 2M and a second layered part nearest to the undersurface of the main part 2M are arranged such that the second faces of he semiconductor chips face each other and the first terminals are composed by using the electrodes in the first layered part and the second terminals are composed by using the electrodes in the second layered part.

Abstract translation: 要解决的问题：为了实现低成本的层压芯片封装，这允许多个层压芯片封装层压并彼此电连接。 解决方案：层压芯片封装1包括：主体2; 主体2包括多于两个的分层部分10，并且具有主体部分2M，其具有尖端面和下表面，多个第一端子4布置在主体部分2M的顶面上，多个第二部分 端子布置在主体2M的下表面上。 层叠部分10包括具有第一表面和第二表面的半导体芯片，以及设置在第一表面侧并连接到布线3的多个电极。最靠近主要部分2M的顶面的第一分层部分和 最靠近主要部分2M的下表面的第二分层部件被布置成半导体芯片的第二面彼此面对，并且第一端子通过使用第一层叠部分中的电极而构成，并且第二端子由使用 第二分层部分中的电极。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2007305667A

公开(公告)日：2007-11-22

申请号：JP2006130339

申请日：2006-05-09

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： NASU ISATO ,  USUI TAKAMASA

IPC: H01L21/60

CPC classification number: H01L24/48 ,  H01L23/3192 ,  H01L23/48 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48757 ,  H01L2224/48847 ,  H01L2224/48857 ,  H01L2224/8112 ,  H01L2224/81801 ,  H01L2224/83907 ,  H01L2224/85447 ,  H01L2224/8547 ,  H01L2224/85909 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48657 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing time and manufacturing cost, and to suppress a drop of yield and reliability in a semiconductor device wherein a semiconductor chip and a lamination body are connected. SOLUTION: The semiconductor device is provided with a semiconductor chip 10 having a first pad 13, a lamination body 20 having a second pad 23 facing the first pad 13, and high melting-point metallic layers 15 and 25 which are directly in contact with the first and second pads 13 and 23, respectively, and are formed by the electroless plating method. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了减少制造时间和制造成本，并且抑制半导体芯片和层压体连接的半导体器件的产率和可靠性的下降。 解决方案：半导体器件设置有具有第一焊盘13的半导体芯片10，具有面向第一焊盘13的第二焊盘23的层叠体20和直接位于第一焊盘13中的高熔点金属层15和25 分别与第一和第二焊盘13和23接触，并通过无电镀方法形成。 版权所有（C）2008，JPO＆INPIT