公开(公告)号：JP5728423B2

公开(公告)日：2015-06-03

申请号：JP2012075803

申请日：2012-03-29

Applicant: 株式会社東芝

Inventor： 山田 浩 ,  小野塚 豊 ,  飯田 敦子 ,  板谷 和彦

IPC: H01L25/04 ,  H01L25/18 ,  H01L23/52 ,  H01L23/12

CPC classification number: H01L25/105 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49572 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L23/5226 ,  H01L24/82 ,  H01L2924/181 ,  H01L2924/3511

公开(公告)号：JP2010538469A

公开(公告)日：2010-12-09

申请号：JP2010523046

申请日：2008-08-21

Applicant: マイクロン テクノロジー, インク.

Inventor： ポー チア，ヤン ,  クワン チュア，スウィー ,  ジュン ブーン，スアン

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/12 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/24227 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/4943 ,  H01L2224/76155 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85045 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00

Abstract: 本明細書では、相互接続を含む半導体デバイスおよびアセンブリ、ならびにそのような相互接続を形成するための方法が開示される。 半導体デバイスを製造する方法の一実施形態は、行および列に配列された複数のダイを有するモールドされたウェーハのモールドされた部分に、中間深度まで複数の第一の面のトレンチを形成するステップを含む。 本方法は、第一の面のトレンチと一直線に合わせた領域におけるモールドされた部分の第二の面から材料を除去するステップをも含み、材料を除去するこのステップは、モールドされた部分を貫通する開口を形成する。 本方法は、モールドされた部分の第二の面において、開口で複数の電気的接点を形成するステップと、第二の面の接点を、ダイ上の対応するボンド部位へと電気的に接続するステップとを、さらに含む。

公开(公告)号：JP4285364B2

公开(公告)日：2009-06-24

申请号：JP2004240466

申请日：2004-08-20

Applicant: パナソニック株式会社

Inventor： 正浩 小野 ,  和宏 西川 ,  一人 西田 ,  繁 近藤

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/02 ,  H05K3/32 ,  H05K3/46

CPC classification number: H05K1/183 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/1627 ,  H01L2924/3511 ,  H05K2201/0382 ,  H05K2201/10674 ,  H05K2201/2018 ,  H05K2203/0278

Abstract: A 3D circuit module which is highly reliable, easily layered and able to mount electronic components in high density is obtained by providing a support member having a frame in the periphery thereof and a recess; a coating layer for coating the frame and filling in the recess, the coating layer being made of resin material which is adhesive and has a softening temperature lower than the softening temperature of the support member; a wiring pattern formed on the coating layer, the wiring pattern including a first land on the frame, a second land on the recess, and a wiring part for connecting between the first land and the second land; and an electronic component having a projecting electrode formed on a side thereof, the electronic component being bonded to the coating layer and accommodated in the recess, with the projecting electrode connected to the second land.

公开(公告)号：JP2004134814A

公开(公告)日：2004-04-30

申请号：JP2004013722

申请日：2004-01-21

Applicant: Legacy Electronics Inc ,  レガシー エレクトロニクス, インコーポレイテッド

Inventor： KLEDZIK KENNETH

IPC: H01L25/00 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/14 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36 ,  H05K13/04

CPC classification number: B23P19/00 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/0002 ,  H05K1/141 ,  H05K3/30 ,  H05K3/303 ,  H05K3/3421 ,  H05K3/3494 ,  H05K3/368 ,  H05K13/0478 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/0195 ,  H05K2203/085 ,  H05K2203/1484 ,  H05K2203/1509 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/52 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53187 ,  Y10T156/1052 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an effective and cost-effective manufacturing process and a device making use of the result of a new development to make it possible to position a chip by a three-dimensional array on a printed circuit substrate. SOLUTION: This method makes use of a unique chip carrier. It employs a manufacturing process of a plurality of processes that automate the surface mounting of a semiconductor chip and achieve the three-dimensional array of a chip. It includes a process of imparting solder to a plurality of chip carriers simultaneously, a process of positioning a chip carrier having a chip on a printed circuit substrate and a process of connecting all the elements eternally after making a chip and a carrier constituted as a three-dimensional array pass a single reflow oven and completing a single reflow process. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2016154233A

公开(公告)日：2016-08-25

申请号：JP2016029576

申请日：2016-02-19

Applicant: スリーディー プラス

Inventor： アレクサンドル・バル ,  ファブリス・スフレ

IPC: H01L25/11 ,  H01L25/18 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/49555 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064

Abstract: 【課題】外部相互接続リードを備える3D電子モジュールを製造するための方法を提供する。 【解決手段】接着剤で組み付けられ、少なくとも1つの電子部品と、パッケージ41および/またはプリント配線基板を電気的に相互接続するための外側タブ42とをそれぞれ備えたパッケージおよび/またはプリント配線基板のスタック40を、変形させることなく成形すべき部分に、パッケージおよび/またはプリント配線基板の外側タブ42を少なくとも部分的に重ね合わせるように、フレームの中心に配置するステップを備える。この目的のために、スタック40は、予め設定された高さの金属、セラミックまたはポリマーからなるパドル50上に配置され、このパドルは、フレームの中心のキャリア30上に、またはフレームの枠組部分上に配置される 【選択図】図2d

Abstract translation: 要解决的问题：提供一种用于制造具有外部互连引线的3D电子模块的方法。解决方案：封装的堆叠40和/或印刷线路板通过粘合剂组装，并且包括至少一个电子部件和 外部接头42，用于电连接封装41和/或印刷线路板。 所述方法包括将所述堆叠设置在框架的中心处，使得所述包装的外部突片42和/或所述印刷线路板至少部分地与所述堆叠的模制部分重叠而不变形。 为此目的，堆叠40设置在由具有预定高度的金属，陶瓷或聚合物形成的桨叶50上，并且桨叶设置在框架中心或框架的框架部分的载体30上。选择 绘图：图2d

公开(公告)号：JP2013140963A

公开(公告)日：2013-07-18

申请号：JP2012281963

申请日：2012-12-26

Applicant: Troisd Plus ,  トロワデー プリュ

Inventor： CHRISTIAN VAL

IPC: H01L25/065 ,  H01L23/12 ,  H01L25/07 ,  H01L25/18 ,  H05K3/00 ,  H05K3/46

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/50 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24141 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/225 ,  H05K3/4688 ,  H05K2201/09981 ,  H05K2201/10674 ,  H05K2203/1327 ,  H01L2224/83 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a method for collective fabrication of a 3D electronic module including only a validated PCB.SOLUTION: The present invention relates to a method for collective fabrication of a 3D electronic module. The method includes the steps of: fabricating a laminate of reconstructed wafers including a validated active component, the laminate including a redistribution layer; fabricating a panel of a validated passive printed circuit board, the step including the following substeps of fabricating a panel of a printed circuit board, performing an electrical test of the printed circuit board, fitting the validated printed circuit board to an adhesive substrate, molding a mounted circuit in an electrically insulating resin called a coating resin and polymerizing the resin, and removing the adhesive substrate to obtain a panel including only a validated printed circuit board; bonding the panel by using a laminate (of reconstructed wafers); and cutting a "laminate-panel" assembly in order to obtain a 3D electronic module.

Abstract translation: 要解决的问题：提供一种用于集体制造仅包括经过验证的PCB的3D电子模块的方法。解决方案：本发明涉及一种用于3D电子模块的集体制造的方法。 该方法包括以下步骤：制造包括经验证的活性组分的重构晶片的层压体，所述层压体包括再分布层; 制造经验证的无源印刷电路板的面板，该步骤包括制造印刷电路板的面板的以下子步骤，执行印刷电路板的电气测试，将经验证的印刷电路板安装到粘合剂基底上，模制 将其安装在称为涂料树脂的电绝缘树脂中并聚合树脂，并除去粘合剂基板以获得仅包含经验证的印刷电路板的面板; 通过使用层压板（重构晶片）来接合面板; 并切割“层叠板”组件以获得3D电子模块。

公开(公告)号：JP2013026615A

公开(公告)日：2013-02-04

申请号：JP2012051467

申请日：2012-03-08

Applicant: Headway Technologies Inc ,  ヘッドウェイテクノロジーズ インコーポレイテッド ,  Sae Magnetics(H K )Ltd ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： SASAKI YOSHITAKA ,  ITO HIROYUKI ,  IKEJIMA HIROSHI ,  IIJIMA ATSUSHI

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/27 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To easily achieve a package at low cost, the package having a function equal to that of a package that does not include a semiconductor chip which does not operate normally even when including a semiconductor chip which does not operate normally.SOLUTION: A composite layered chip package 1 includes a plurality of subpackages 1A-1E. Each of the subpackages includes a body and wiring. The body has a main part including a plurality of layer portions 10, and a first terminal and a second terminal arranged on the upper surface and the lower surface of the main part, respectively. The wiring is connected to the first and second terminals. In all of the subpackages, the number of the layer portions 10 is equal, and the plurality of layered portions 10 include at least one first type layer portion. In at least two of the plurality of subpackages, the plurality of layer portions 10 further include a second type layer portion. A semiconductor chip of the first type layer portion is connected to the wiring, and a semiconductor chip of the second type layer portion is not connected to the wiring.

Abstract translation: 要解决的问题为了容易地以低成本实现封装，封装具有与不包括半导体芯片的功能相同的功能，即使在包括不工作的半导体芯片的情况下也不能正常工作 一般。 复合分层芯片封装1包括多个子封装1A-1E。 每个子包包括一个主体和接线。 主体具有包括多个层部分10的主要部分和分别布置在主要部分的上表面和下表面上的第一端子和第二端子。 接线连接到第一和第二端子。 在所有子部件中，层部10的数量相等，多个分层部10至少包括一个第一类型的层部。 在多个子包中的至少两个子包中，多层层10还包括第二类型层部分。 第一型层部分的半导体芯片连接到布线，并且第二类型层部分的半导体芯片没有连接到布线。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012190833A

公开(公告)日：2012-10-04

申请号：JP2011050472

申请日：2011-03-08

Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

Inventor： ARAKI SHINTARO ,  OKAMOTO YOSHIHIDE ,  KHALID HASSAN HUSSEIN ,  AIKO MITSUNORI

IPC: H01L25/10 ,  H01L25/18 ,  H02M7/48

CPC classification number: H02M7/003 ,  H01L23/3107 ,  H01L25/112 ,  H01L2225/1011 ,  H01L2225/1064 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a power module which reduces its size by avoiding the use of bus bars.SOLUTION: A power module according to this invention has a collector terminal extending from a mold resin to the exterior and an emitter terminal extending from the mold resin to the exterior. At least one of the collector terminal and the emitter terminal includes: a first semiconductor device which extends from opposing two surfaces of the mold resin to the exterior and serves as a both side extending terminal; and a second semiconductor device having the same structure as the first semiconductor device. The both side extending terminal of the first semiconductor device and the both side extending terminal of the second semiconductor device are connected with each other.

Abstract translation: 要解决的问题：提供一种通过避免使用母线来减小其尺寸的电源模块。 解决方案：根据本发明的功率模块具有从模制树脂延伸到外部的集电极端子和从模制树脂延伸到外部的发射极端子。 集电极端子和发射极端子中的至少一个包括：第一半导体器件，其从模制树脂的相对的两个表面延伸到外部并用作​​两侧延伸端子; 以及具有与第一半导体器件相同结构的第二半导体器件。 第一半导体器件的两侧延伸端子和第二半导体器件的两侧延伸端子彼此连接。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012520558A

公开(公告)日：2012-09-06

申请号：JP2011553423

申请日：2010-03-09

Applicant: トロワデー、プリュ3D Plus

Inventor： ヴァル、クリスチャン

IPC: H01L23/29 ,  H01L23/12 ,  H01L23/31 ,  H01L23/40

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/4334 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/24137 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

公开(公告)号：JP2012080067A

公开(公告)日：2012-04-19

申请号：JP2011106803

申请日：2011-05-12

Applicant: Headway Technologies Inc ,  Sae Magnetics(H.K.)Ltd ,  ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： SASAKI YOSHITAKA ,  ITO HIROYUKI ,  IKEJIMA HIROSHI ,  IIJIMA ATSUSHI

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L22/22 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014

Abstract: PROBLEM TO BE SOLVED: To achieve a package that is capable of stacking a plurality of stacked chip packages and electrically connecting one another in a simple structure and includes the desired number of semiconductor chips at a low cost.SOLUTION: A stacked chip package 1S comprises: a body 2; and a wiring layer 3 including a plurality of wires W disposed on the side surfaces of the body 2. The body 2 has a main portion 2M including two layer portions 10S1 and 10S2, and a plurality of first and second terminals 4 and 5 that are disposed on the top surface and the bottom surface of the main portion 2M and are connected to the plurality of wires W. The first and second terminals 4 and 5 are constituted using electrodes of the layer portions 10S1 and 10S2. The stacked chip package 1S is manufactured such that a stacked substructure is manufactured by stacking two substructures including a plurality of arranged auxiliary layer portions, and then the stacked substructure is cut. The stacked substructure is disposed between two adjacent bodies before separation and includes a plurality of auxiliary wires to be a plurality of wires later.

Abstract translation: 要解决的问题：为了实现能够堆叠多个堆叠的芯片封装并且以简单的结构彼此电连接并且以低成本包括所需数量的半导体芯片的封装。 解决方案：堆叠式芯片封装1S包括：主体2; 以及配置在主体2的侧面上的多个布线W的布线层3.主体2具有包括两层部10S1，10S2的主体部2M和多个第一，第二端子4,5， 设置在主体部分2M的上表面和下表面上并连接到多条电线W.第一和第二端子4,5由层部分10S1和10S2的电极构成。 制造堆叠的芯片封装1S，使得通过堆叠包括多个布置的辅助层部分的两个子结构来制造堆叠的子结构，然后切割堆叠的子结构。 堆叠的子结构在分离之前设置在两个相邻的主体之间，并且包括多个辅助线，其后面将成为多个线。 版权所有（C）2012，JPO＆INPIT