公开(公告)号：JP5563814B2

公开(公告)日：2014-07-30

申请号：JP2009287903

申请日：2009-12-18

Applicant: 新光電気工業株式会社

Inventor： 翔太 三木

IPC: H01L23/12 ,  H01L21/301

CPC classification number: H01L24/96 ,  H01L23/16 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1319 ,  H01L2224/13611 ,  H01L2224/2402 ,  H01L2224/2405 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

公开(公告)号：JP2014123736A

公开(公告)日：2014-07-03

申请号：JP2013263323

申请日：2013-12-20

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社Samsung Electronics Co.,Ltd.

Inventor： KIM KEEL SOO ,  KANG SUN-WON

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package having improved electrical characteristics.SOLUTION: A semiconductor package according to the present embodiment comprises a package substrate having an opening at the center and a circuit pattern adjacent to the opening; a first semiconductor chip which is arranged above the package substrate and has first bonding pads; a pair of second semiconductor chips which are mounted between the package substrate and the first semiconductor chip and has second bonding pads, respectively, and which are arranged at a distance from each other; and connection members for electrically connecting the first bonding pads with the second bonding pads, respectively.

Abstract translation: 要解决的问题：提供具有改善的电特性的半导体封装。解决方案：根据本实施例的半导体封装包括在中心具有开口的封装基板和与开口相邻的电路图案; 第一半导体芯片，其布置在封装衬底上方并具有第一焊盘; 一对第二半导体芯片，分别安装在封装基板和第一半导体芯片之间，并且分别具有第二接合焊盘，并且彼此间隔一定距离; 以及用于将第一接合焊盘与第二接合焊盘电连接的连接构件。

公开(公告)号：JP5305148B2

公开(公告)日：2013-10-02

申请号：JP2008512023

申请日：2007-03-15

Applicant: 株式会社村田製作所

Inventor： 達弥 舟木

IPC: H01L21/60

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0331 ,  H01L2224/03505 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11505 ,  H01L2224/1155 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/16501 ,  H01L2224/245 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/76155 ,  H01L2224/81055 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81379 ,  H01L2224/81594 ,  H01L2224/81639 ,  H01L2224/81801 ,  H01L2224/8184 ,  H01L2224/8284 ,  H01L2224/8384 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/19041 ,  Y10S977/779 ,  H01L2924/00014 ,  H01L2924/0543 ,  H01L2924/20107 ,  H01L2924/01014

Abstract: There are provided an electronic element having a connection portion at which an electrode having a surface composed of at least Al or an alloy and a metal nanoparticle sintered body is connected to each other, an electronic element device using the same, and a manufacturing method thereof. In an electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode, a bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the constituent element of the metal nanoparticles.

公开(公告)号：JPWO2010087336A1

公开(公告)日：2012-08-02

申请号：JP2010548518

申请日：2010-01-26

Applicant: パナソニック株式会社

Inventor： 愼悟 吉岡 ,  愼悟 吉岡 ,  弘明 藤原 ,  弘明 藤原

IPC: H01L21/60 ,  H01L23/52

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: 本発明の一局面は、半導体チップ2の表面のボンディングパッド2aと絶縁基材1の表面に形成された電極パッド1aとをつなぐ経路の表面に樹脂被膜3を形成する工程と、ボンディングパッド2aと電極パッド1aとを接続するための経路に沿って、樹脂被膜3の厚みと同じまたは厚み分以上の深さの配線溝4をレーザー加工により形成する工程と、配線溝4の表面にメッキ触媒5を被着させる工程と、樹脂被膜3を除去する工程と、メッキ触媒5が残留する部位のみに無電解メッキ膜6を形成する工程とを備える半導体チップの実装方法である。本発明の他の一局面は、表面に配線が設けられた立体構造物であって、立体構造物の表面に、立体構造物の相互に交差する隣接面間に亘って延びる配線用凹溝が形成され、前記配線用凹溝の中に配線用導体の少なくとも一部が埋め込まれていることを特徴とする立体構造物である。

公开(公告)号：JP2012009808A

公开(公告)日：2012-01-12

申请号：JP2011011788

申请日：2011-01-24

Applicant: Headway Technologies Inc ,  Sae Magnetics (Hk) Ltd ,  ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： SASAKI YOSHITAKA ,  ITO HIROYUKI ,  IIJIMA ATSUSHI

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0392 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83121 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method that facilitates performing the package inspection for the whole individual chip and enables to increase the number of laminated chip packages manufacturable per unit time by reducing the manufacturing time.SOLUTION: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts 21A formed along scribe lines 3A, 3B. Further, each of the semiconductor substrate has a semiconductor device formed therein, and has a plurality of device regions insulated from each other, and a first wiring electrode and a second wiring electrode extend to the inside of a interposed scribe-groove part from a first device region and a second device region adjacent to each other via the scribe groove part respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole in which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is in contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.

Abstract translation: 要解决的问题：为了提供便于对整个单个芯片执行封装检查的方法，并且能够通过减少制造时间来增加每单位时间制造的层压芯片封装的数量。 解决方案：在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线3A，3B形成的多个划线槽部分21A。 此外，每个半导体基板具有形成在其中的半导体器件，并且具有彼此绝缘的多个器件区域，并且第一布线电极和第二布线电极从第一布线电极延伸到插入的划线槽部分的内部 装置区域和通过划线槽部分相邻的第二装置区域，并且彼此分离。 在层叠半导体基板中，形成有第一布线电极出现的通孔。 层叠半导体基板具有贯通电极。 通孔与通孔中出现的所有第一布线电极接触。 层叠半导体衬底具有多个层叠芯片区域。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011129767A

公开(公告)日：2011-06-30

申请号：JP2009287903

申请日：2009-12-18

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： MIKI SHOTA

IPC: H01L23/12 ,  H01L21/301

CPC classification number: H01L24/96 ,  H01L23/16 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1319 ,  H01L2224/13611 ,  H01L2224/2402 ,  H01L2224/2405 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device that allows adoption of a so-called fan-out structure.
SOLUTION: The manufacturing method for a semiconductor device has a first to sixth steps of: (1) forming a first electrode pad 26 at the outer edge of a semiconductor chip mounting region D of a support substrate 14; (2) fixing the rear surface of a semiconductor chip 11 to the inside of the region formed with the first electrode pad; (3) forming a first internal connection terminal 12 and a second internal connection terminal 15 respectively on the first electrode pad 26 and a second electrode pad 23; (4) forming a first insulating layer 16 covering the semiconductor chip 11 and partially exposing the first internal connection terminal 12 and the second internal connection terminal 15; (5) forming a wiring pattern 17, electrically connecting the first internal connection terminal with the second internal connection terminal, on the first insulating layer 16; and forming a second insulating layer 18 having an opening that exposes an external connection terminal arrangement region 17A of the wiring pattern. The opening is arranged in a region including a region outside the second internal connection terminal.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种允许采用所谓扇出结构的半导体器件的制造方法。 解决方案：半导体器件的制造方法具有第一至第六步骤：（1）在支撑衬底14的半导体芯片安装区域D的外边缘处形成第一电极焊盘26; （2）将半导体芯片11的后表面固定在形成有第一电极焊盘的区域的内部; （3）分别在第一电极焊盘26和第二电极焊盘23上形成第一内部连接端子12和第二内部连接端子15; （4）形成覆盖半导体芯片11的第一绝缘层16并且部分地暴露第一内部连接端子12和第二内部连接端子15; （5）在第一绝缘层16上形成将第一内部连接端子与第二内部连接端子电连接的布线图案17; 以及形成具有露出布线图案的外部连接端子排列区域17A的开口的第二绝缘层18。 开口布置在包括第二内部连接端子外部的区域的区域中。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP6219929B2

公开(公告)日：2017-10-25

申请号：JP2015507201

申请日：2013-04-19

Applicant: レンセレイアー ポリテクニック インスティテュート

Inventor： ロバート エフ.カーリセック ,  ジェイムズ ジエン−チアーン ルー ,  チャールズ サンフォード グッドウィン ,  アントン トカチェンコ

IPC: H01L33/48

CPC classification number: H01L25/50 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/75 ,  H01L24/76 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0753 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/04026 ,  H01L2224/05655 ,  H01L2224/13101 ,  H01L2224/24225 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/75655 ,  H01L2224/75701 ,  H01L2224/75733 ,  H01L2224/75801 ,  H01L2224/76655 ,  H01L2224/76701 ,  H01L2224/76733 ,  H01L2224/76801 ,  H01L2224/82002 ,  H01L2224/82102 ,  H01L2224/82143 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/8323 ,  H01L2224/83801 ,  H01L2224/9202 ,  H01L2224/95101 ,  H01L2224/95144 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/3511 ,  H01L2933/0066

公开(公告)号：JP6045243B2

公开(公告)日：2016-12-14

申请号：JP2012171731

申请日：2012-08-02

Applicant: ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司 ,  SAE Magnetics(H.K.)Ltd.

Inventor： 佐々木 芳高 ,  伊藤 浩幸 ,  種村 茂樹 ,  佐藤 一樹 ,  飯島 淳

IPC: H01L25/07 ,  H01L25/18 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L24/83 ,  H01L24/94 ,  H01L2924/07802 ,  H01L2924/12042

公开(公告)号：JP2013539925A

公开(公告)日：2013-10-28

申请号：JP2013533871

申请日：2011-09-26

Applicant: インヴェンサス・コーポレイション

Inventor： バリー，キース・レイク ,  パングル，シュゼット・ケイ ,  ビリャビセンシオ，グラント ,  リール，ジェフリー・エス

IPC: H01L21/60 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/83 ,  H01L23/293 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/038 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/1131 ,  H01L2224/11848 ,  H01L2224/13017 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13347 ,  H01L2224/16145 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/24992 ,  H01L2224/24997 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/831 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to bleed laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

公开(公告)号：JP5154667B2

公开(公告)日：2013-02-27

申请号：JP2011010371

申请日：2011-01-21

Applicant: ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

Inventor： 芳高 佐々木 ,  浩幸 伊藤 ,  寛 池島 ,  淳 飯島

IPC: H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/522 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2746 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2221/68304

Abstract: A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip.