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    Laminated chip package, semiconductor substrate, and method of manufacturing laminated chip package
    44.
    发明专利
    Laminated chip package, semiconductor substrate, and method of manufacturing laminated chip package 有权
    层压芯片封装，半导体基板及制造层压芯片封装的方法

    公开(公告)号：JP2011091360A

    公开(公告)日：2011-05-06

    申请号：JP2010121563

    申请日：2010-05-27

    申请人： Headway Technologies Inc ,  Sae Magnetics (Hk) Ltd ,  ヘッドウェイテクノロジーズ インコーポレイテッド ,  新科實業有限公司SAE Magnetics(H.K.)Ltd.

    发明人： SASAKI YOSHITAKA ,  ITO HIROYUKI ,  IIJIMA ATSUSHI

    IPC分类号： H01L25/065 ,  H01L21/60 ,  H01L23/52 ,  H01L25/07 ,  H01L25/18

    CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L23/585 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06551

    摘要： PROBLEM TO BE SOLVED: To provide a laminated chip package having a structure that facilitates an inspection process for contact resistance and enables the inspection process to be efficiently carried out, to provide a semiconductor substrate for manufacturing the laminated chip package, and to provide a method of manufacturing the laminated chip package. SOLUTION: The laminated chip package is constituted by laminating a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device. The laminated chip package has an end face of an internal electrode for inspection, formed inside a side face for wiring of a semiconductor plate, formed on a side face for wiring. Further, the laminated chip package has an external electrode for inspection, connecting end faces of internal electrodes for inspection to each other along the lamination direction of the semiconductor plates, targeting two adjacent semiconductor plates among the semiconductor plates. COPYRIGHT: (C)2011,JPO&INPIT

    摘要翻译： 解决问题的方案为了提供具有便于接触电阻的检查处理的结构的层叠芯片封装，能够有效地进行检查处理，提供用于制造层叠芯片封装的半导体基板，并且 提供一种制造层压芯片封装的方法。 解决方案：层压芯片封装通过层叠多个半导体器件和半导体器件连接的半导体器件和布线电极的半导体板构成。 层叠芯片封装具有形成在用于布线的侧面上的半导体板的布线用侧面内的检查用内部电极的端面。 此外，层压芯片封装具有用于检查的外部电极，沿着半导体板的层叠方向将用于检查的内部电极的端面彼此连接，靶向半导体板中的两个相邻的半导体板。 版权所有（C）2011，JPO＆INPIT

    Semiconductor device, and method of manufacturing the same
    47.
    发明专利
    Semiconductor device, and method of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：JP2011044594A

    公开(公告)日：2011-03-03

    申请号：JP2009192022

    申请日：2009-08-21

    申请人： Mitsubishi Electric Corp ,  三菱電機株式会社

    发明人： OKUMURA MIKA ,  HORIKAWA MAKIO ,  MURAKAMI TAKASHI

    IPC分类号： H01L21/3205 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13055 ,  H01L2924/00

    摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a through electrode, can be stacked in a longitudinal direction and can increase the degree of freedom of design, and to provide a method of manufacturing the semiconductor device. SOLUTION: The semiconductor device includes a semiconductor substrate 1, an electrode 30a and an electrode 30b provided apart from each other from a first principal surface 10 along a depth of the semiconductor substrate 1, and a wiring portion 40a connecting the electrodes 30a and electrode 30b to each other and provided from the first principal surface 10 along the depth of the semiconductor substrate 1 without penetrating the semiconductor substrate 1. The electrode 30a is the through hole penetrating the semiconductor substrate 1 to reach a second principal surface 20. The semiconductor device which has the through hole and is stacked in the longitudinal direction has the wiring portion 40a, so as to increase the degree of freedom of design. COPYRIGHT: (C)2011,JPO&INPIT

    摘要翻译： 要解决的问题：为了提供一种具有通孔的半导体器件，可以在纵向上堆叠并且可以增加设计的自由度，并且提供一种制造半导体器件的方法。 解决方案：半导体器件包括半导体衬底1，电极30a和沿着半导体衬底1的深度与第一主表面10彼此分开设置的电极30b以及连接电极30a的布线部分40a 电极30b彼此连接，并且不沿着半导体基板1的深度从第一主表面10提供，而不穿透半导体基板1.电极30a是贯穿半导体基板1到达第二主表面20的通孔。 具有通孔并沿纵向层叠的半导体器件具有布线部分40a，以增加设计的自由度。 版权所有（C）2011，JPO＆INPIT

    Suppressing fracture in diced integrated circuit
    48.
    发明专利
    Suppressing fracture in diced integrated circuit 审中-公开
    DICED集成电路中的抑制断裂

    公开(公告)号：JP2011018906A

    公开(公告)日：2011-01-27

    申请号：JP2010155424

    申请日：2010-07-08

    申请人： Lsi Corp ,  エルエスアイ コーポレーション

    发明人： BACHMAN MARK A ,  OSENBACH JOHN W

    IPC分类号： H01L21/3205 ,  H01L21/301 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

    CPC分类号： H01L23/585 ,  H01L23/3128 ,  H01L23/5329 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

    摘要： PROBLEM TO BE SOLVED: To suppress loss of yield and initial failure of ICs that uses low dielectric constant dielectrics.SOLUTION: A semiconductor device has a substrate 210 and a die 110, which has an edge of die and being broken into pieces. Interconnection dielectric layers 220a, 220b, 220c, and 220d are arranged on the substrate and an integrated circuit has interconnection sections 230 arranged in the interconnection dielectric layers. A trench 250 is disposed in the interconnection dielectric layers between a seal ring 270 and the remaining interconnection dielectric layers. The seal ring is arranged in the interconnection dielectric layers between the trench and the integrated circuit, and the remaining portion of the interconnection dielectric layers is arranged between the trench and the edge of the die.

    摘要翻译： 要解决的问题：抑制使用低介电常数电介质的IC的产量损失和初始故障。解决方案：半导体器件具有衬底210和裸片110，其具有裸片的边缘并被分解成片。 互连电介质层220a，220b，220c和220d布置在衬底上，并且集成电路具有布置在互连电介质层中的互连部分230。 沟槽250布置在密封环270和剩余的互连电介质层之间的互连电介质层中。 密封环布置在沟槽和集成电路之间的互连电介质层中，并且互连电介质层的剩余部分布置在沟槽和管芯的边缘之间。

    Method of manufacturing semiconductor device, semiconductor chip, and semiconductor wafer
    49.
    发明专利
    Method of manufacturing semiconductor device, semiconductor chip, and semiconductor wafer 有权
    制造半导体器件，半导体芯片和半导体器件的方法

    公开(公告)号：JP2011003674A

    公开(公告)日：2011-01-06

    申请号：JP2009144645

    申请日：2009-06-17

    申请人： Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

    发明人： UCHIDA SHINICHI ,  KAWASHIMA YOSHITSUGU ,  ISE HIROSHI

    IPC分类号： H01L21/66 ,  H01L21/301 ,  H01L21/3205 ,  H01L23/52

    CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： PROBLEM TO BE SOLVED: To provide a technique for aiming at gaining both of suppression of an increase in impedance of connection wiring and improvement in dicing properties of a semiconductor wafer.SOLUTION: In the semiconductor wafer 1, a plurality of wiring layers are formed, a plurality of chip constitution sections 2 that become semiconductor chips including one portion of the plurality of respective wiring layers are formed, and the mutually adjacent chip constitution sections 2 are connected mutually and electrically via connection wiring 3 included in any one of the wiring layers. The connection wiring 3 is formed so that a middle section 3b positioned between connection ends 3a is narrower than the connection ends 3a to the chip constitution section 2 in the connection wiring 3. A semiconductor chip is formed by mutually separating the chip constitution sections 2 by cutting the semiconductor wafer 1 along a scribe line 4 extended to cross the connection wiring 3 between the mutually adjacent chip constitution sections 2.

    摘要翻译： 要解决的问题：提供一种用于获得抑制连接布线的阻抗增加和提高半导体晶片的切割性能的技术。解决方案：在半导体晶片1中，形成多个布线层， 形成成为包含多个各个布线层的一部分的半导体芯片的多个芯片结构部分2，并且相互相邻的芯片构成部分2通过包括在任何一个布线层中的连接布线3相互电连接。 连接布线3形成为使得位于连接端3a之间的中间部分3b比连接布线3中的连接端3a至芯片结构部分2窄。通过将芯片结构部分2相互分离形成半导体芯片 沿着与相邻的芯片构成部分2之间的连接布线3延伸的划线4切割半导体晶片1。