公开(公告)号：JP2007208263A

公开(公告)日：2007-08-16

申请号：JP2007021348

申请日：2007-01-31

Applicant: Samsung Electro Mech Co Ltd ,  三星電機株式会社

Inventor： JUNG HYUNG MI ,  CHUNG YUL KYO ,  KANG HYOUNG DONG

IPC: H05K3/46 ,  H01G4/12 ,  H01G4/33

CPC classification number: H05K1/162 ,  H05K3/16 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed-circuit substrate with a built-in thin-film capacitor.
SOLUTION: This method for manufacturing the printed-circuit substrate with the built-in thin-film capacitor comprises a process to form a bottom electrode 120 by spattering conductive metal on an insulator substrate 110 using a first mask, process to form a dielectric layer 130 surrounding part of the bottom electrode and its one side end by spattering dielectric material on the bottom electrode using a second mask, process to form an upper electrode 150 by spattering conductive metal on the dielectric layer and a substrate that touches the dielectric layer using a third mask, process to form via holes between the surface of an insulating layer 170 and the bottom electrode after the insulating layer is piled on a lamination formed with the upper electrode and also between the surface of the insulating layer and the upper electrode formed on the substrate, and process to perform non-electrolytic and electrolytic copper plating on the lamination where the via holes are formed.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于制造具有内置薄膜电容器的印刷电路基板的方法。 解决方案：用于制造具有内置薄膜电容器的印刷电路基板的该方法包括通过使用第一掩模在绝缘体基板110上溅射导电金属来形成底部电极120的工艺，以形成 通过使用第二掩模在底部电极上溅射电介质材料来围绕底部电极的一部分并且其一个侧端的介电层130，通过在电介质层上溅射导电金属和接触电介质层的基板来形成上部电极150 使用第三掩模，在将绝缘层堆叠在由上电极形成的层压体之后，以及形成绝缘层和上电极的表面之间，在绝缘层170的表面和底电极之间形成通孔的工艺 并且在形成通孔的叠层上进行非电解和电解镀铜处理。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007518222A

公开(公告)日：2007-07-05

申请号：JP2006546010

申请日：2004-12-17

Applicant: アルカン テヒノロギー ウント メーニッジメント リミテッドAlcan Technology & Management Ltd.

Inventor： ツィーグラー アンドレアス ,  ハモン ヴェルナー ,  ローヴァッサー ヴォルフガング ,  デル ノーマン ,  ラインホルト マティアス ,  リューティ マルクス

IPC: H01B7/04 ,  H01B7/08 ,  H01B7/282 ,  H01B11/06 ,  H05K1/00 ,  H05K1/02 ,  H05K3/12 ,  H05K3/20 ,  H05K3/24 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K3/245 ,  H01B7/0861 ,  H05K1/0393 ,  H05K3/12 ,  H05K3/207 ,  H05K3/281 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0179 ,  H05K2201/0715 ,  H05K2201/098 ,  H05K2203/0113 ,  H05K2203/1476

Abstract: 合成樹脂製の基材層（１２）と、前記基材層の少なくとも一つの側面に導電性塗料が沈着された、少なくとも一つの導電性構造体（２０）とを有する、可撓性キャリア（１０）である。 前記少なくとも一つの導電性構造体（２０）は、基材層（１２）と、少なくとも一つの合成樹脂製の上張り層（１４）との間に配置される。 選択的に形成可能な更に他の複数の導電性構造体（２２）は、それぞれ、選択的に形成可能な更に他の上張り層の間に配置される。 基材層（１２）は上張り層（１４）に一体化され、選択的に形成された前記更に他の導電性構造体（２２）は、それぞれ、隣接する上張り層に一体化される。

公开(公告)号：JP2007157835A

公开(公告)日：2007-06-21

申请号：JP2005348044

申请日：2005-12-01

Applicant: Matsushita Electric Ind Co Ltd ,  松下電器産業株式会社

Inventor： YANAGIHARA MANABU ,  UENO HIROAKI ,  UEMOTO YASUHIRO ,  TANAKA TAKESHI

IPC: H01L23/12 ,  H01L23/36

CPC classification number: H05K3/28 ,  H01L21/563 ,  H01L23/3732 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0209 ,  H05K2201/0179 ,  H05K2201/0323 ,  H05K2201/09045 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To obtain a light-weight and small-sized mounting substrate for mounting a power device chip or a power device package by improving heat radiating property. SOLUTION: Through-holes 18 are formed to an insulating substrate 17 and are filled with a metal material. On these through-holes, a diamond film 16 is formed, and a surface-mounting power device 11, formed of GaN in its semiconductor material of an active layer, is mounted. In this case, heat from the power device 11 is diffused to the front surface of the insulating substrate 17 through the diamond film 16 having higher heat conductivity. The heat is then diffused to a heat radiating plate 16 through the metal material filling the through-holes 18. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过改善散热性能来获得用于安装功率器件芯片或功率器件封装的重量轻的小型安装基板。 解决方案：将通孔18形成在绝缘基板17上并填充有金属材料。 在这些通孔上形成金刚石膜16，并且安装由GaN在其有源层的半导体材料中形成的表面安装功率器件11。 在这种情况下，来自功率器件11的热量通过具有较高导热性的金刚石膜16扩散到绝缘衬底17的前表面。 然后，热量通过填充通孔18的金属材料扩散到散热板16上。（C）2007，JPO＆INPIT

公开(公告)号：JP2007134711A

公开(公告)日：2007-05-31

申请号：JP2006301545

申请日：2006-11-07

Applicant: Samsung Electro Mech Co Ltd ,  三星電機株式会社

Inventor： MOON JIN SEOK ,  CHUNG YUL KYO ,  LYOO SOO HYUN ,  SOHN SEUNG HYUN

IPC: H05K1/16 ,  H01G4/12 ,  H01G4/33

CPC classification number: H05K1/162 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  Y10T29/417 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board incorporating a thin film capacitor capable of forming an amorphous paraelectric thin film having desired dielectric characteristics at a low temperature and capable of improving reliability of products, and a manufacturing method of the same. SOLUTION: A printed circuit board 30 is provided, with a thin film capacitor incorporated therein, sequentially including: a lower electrode 33 on an insulating base material 31a; an amorphous paraelectric film 35 formed on the lower electrode; a metal seed layer 37 formed on the paraelectric film; and an upper electrode 39 with surface roughness Ra of 300 nm or more formed on the metal seed layer. In this case, the lower electrode 33 includes a part 33a formed by electroless plating and a part 33b formed by electrolytic plating. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种结合了能够形成具有期望的介电特性的低温非晶质顺电薄膜并且能够提高产品的可靠性的薄膜电容器的印刷电路板及其制造方法 。

解决方案：提供印刷电路板30，其中并入有薄膜电容器，其顺序包括：在绝缘基材31a上的下电极33; 形成在下电极上的非晶顺电膜35; 形成在顺电膜上的金属种子层37; 以及形成在金属种子层上的表面粗糙度Ra为300nm以上的上部电极39。 在这种情况下，下电极33包括通过无电镀形成的部分33a和通过电解电镀形成的部分33b。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007126354A

公开(公告)日：2007-05-24

申请号：JP2006272931

申请日：2006-10-04

Applicant: Samsung Electro Mech Co Ltd ,  三星電機株式会社

Inventor： BAE JUN HEE ,  KIN SHOKEN ,  CHUNG YUL KYO ,  SONG WON HOON ,  LIM SUNG TAEK ,  JIN HYUN JU

IPC: C01G23/053 ,  H01B3/00 ,  H01B19/00 ,  H01G4/33 ,  H01L21/316 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01G4/1218 ,  H01G4/33 ,  H01L21/316 ,  H05K2201/0175 ,  H05K2201/0179

Abstract: PROBLEM TO BE SOLVED: To provide a coating solution for the preparing of a high dielectric constant thin film and a preparing method for the dielectric thin film using the coating solution.
SOLUTION: The coating solution comprises a titanium alkoxide, a beta-diketone or its derivative, and a benzoic acid derivative having an electron donating group. The method comprises spin coating the coating solution on a substrate to form a thin film and drying the thin film at a low temperature to crystallize the thin film. The titanium-containing coating solution is highly stable. In addition, the coating solution achieves the formation of a thin film at a low temperature, regardless of the kind of substrates, and can be used to form dielectric thin films in an in-line mode in the production processes of PCBs.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于制备高介电常数薄膜的涂布溶液和使用该涂布溶液的电介质薄膜的制备方法。 溶液：包衣溶液包含钛醇盐，β-二酮或其衍生物，以及具有给电子基团的苯甲酸衍生物。 该方法包括将涂布溶液旋涂在基材上以形成薄膜，并在低温下干燥薄膜以使薄膜结晶。 含钛涂层溶液高度稳定。 此外，涂布溶液在低温下实现薄膜的形成，而不管基板的种类如何，并且可以用于在PCB的生产过程中以在线模式形成电介质薄膜。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007110127A

公开(公告)日：2007-04-26

申请号：JP2006277769

申请日：2006-10-11

Applicant: Samsung Electro Mech Co Ltd ,  三星電機株式会社

Inventor： KO MIN JI ,  CHUNG YUL KYO ,  PARK EUN TAE

IPC: H01G4/33

CPC classification number: H01G4/1218 ,  H01G4/1245 ,  H01G4/33 ,  H05K1/09 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2203/0353 ,  H05K2203/0369

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin film capacitor capable of preventing the oxidization of a lower electrode, preventing a defect at a boundary face between the lower electrode and a dielectric layer, and securing a BDV property, and to provide a printed-circuit substrate in which the thin film capacitor is built.
SOLUTION: The method of manufacturing a thin film capacitor comprises steps of carrying out the recrystallization and the heat treatment of a metallic wheel, forming a dielectric layer on the upper portion of the recrystallized and heat-treated metallic wheel, carrying out the heat treatment of the metallic wheel and the dielectric layer, and forming an upper electrode on the upper portion of the heat-treated dielectric film. In this case, since the recrystallization is carried out at a low temperature in a short time, the recrystallization of the metallic wheel is carried out while preventing the oxidation of the metallic wheel. Thus, the high-temperature heat treatment of the dielectric film is made possible. This improves the electric property of the thin film capacitor and the reliability of a product.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种制造能够防止下部电极氧化的薄膜电容器的方法，防止下部电极和电介质层之间的边界面处的缺陷，并且确保BDV特性， 并且提供其中构建薄膜电容器的印刷电路基板。 解决方案：制造薄膜电容器的方法包括以下步骤：执行金属轮的再结晶和热处理，在再结晶和热处理的金属轮的上部形成电介质层，执行 金属轮和电介质层的热处理，以及在热处理电介质膜的上部形成上电极。 在这种情况下，由于在短时间内在低温下进行再结晶，所以在防止金属轮的氧化的同时进行金属轮的再结晶。 因此，能够进行电介质膜的高温热处理。 这提高了薄膜电容器的电性能和产品的可靠性。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007042989A

公开(公告)日：2007-02-15

申请号：JP2005227798

申请日：2005-08-05

Applicant: Ibiden Co Ltd ,  イビデン株式会社

Inventor： TSUKADA KIYOTAKA

IPC: H05K1/16 ,  H05K1/09

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01G4/1218 ,  H05K1/162 ,  H05K3/025 ,  H05K3/143 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09763

Abstract: PROBLEM TO BE SOLVED: To provide a thin film embedded capacitance having a large electric capacitance per unit, and to provide its manufacturing method. SOLUTION: The thin film embedded capacitance comprises a metal thin film 2P for wiring comprising a metal material in an unyielded state; a first electrode 4 formed on the metal thin film for wiring; a dielectric material layer 6 formed by a sputtering method on the first electrode and the metal thin film for wiring at a temperature not lower than room temperature, and at lower than the yielding temperature of the metal thin film for wiring, and having a smaller coefficient of thermal expansion than that of the metal thin film wiring; and a second electrode 8 formed on the dielectric material layer. Its manufacturing method is also provided. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供每单位具有大电容量的薄膜嵌入式电容器，并提供其制造方法。 解决方案：薄膜嵌入电容包括用于布线的金属薄膜2P，其包括处于非屏蔽状态的金属材料; 形成在用于布线的金属薄膜上的第一电极4; 通过溅射法在第一电极上形成的电介质层6和用于布线的金属薄膜，其温度不低于室温，低于布线金属薄膜的屈服温度，并且具有较小的系数 的热膨胀比金属薄膜布线; 以及形成在电介质材料层上的第二电极8。 还提供其制造方法。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006339158A

公开(公告)日：2006-12-14

申请号：JP2006153256

申请日：2006-06-01

Applicant: Samsung Electro Mech Co Ltd ,  三星電機株式会社

Inventor： SONG WON HOON ,  CHUNG YUL KYO ,  KANG HYOUNG DONG ,  LIM SEONG-TAEK

IPC: H01B19/00 ,  C01G23/04 ,  C01G25/00 ,  H01B3/00 ,  H01B3/12 ,  H01G4/33 ,  H01L21/316 ,  H01L23/12

CPC classification number: H01L21/31691 ,  H01L21/02186 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/02356 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2203/0786 ,  H05K2203/1105

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a crystalline dielectric thin film for forming the crystalline dielectric thin film at a low temperature of 300°C or lower.
SOLUTION: The manufacturing method of a crystalline dielectric thin film includes a stage for forming an amorphous dielectric thin film on a substrate, and a stage for dipping the amorphous dielectric thin film into water for hydrothermal treatment. The stage for forming the amorphous dielectric thin film includes a stage for coating the substrate with amorphous dielectric sol, and a stage for baking the coated crystalloidal dielectric sol. A stage for drying a baked resultant structure after baking can be included further. Coating and baking can be repeated for a number of times for obtaining a thin film having a desired thickness.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在300℃或更低的低温下形成结晶电介质薄膜的结晶电介质薄膜的制造方法。 解决方案：晶体介电薄膜的制造方法包括在基板上形成非晶电介质薄膜的阶段，以及将非晶电介质薄膜浸入水热处理的阶段。 用于形成非晶介质薄膜的阶段包括用非晶介质溶胶涂覆基板的阶段，以及用于烘烤涂覆的晶体介电溶胶的阶段。 焙烧后的烘烤后的结构体的干燥阶段可以进一步包含。 可以重复涂覆和烘烤多次以获得具有所需厚度的薄膜。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006179856A

公开(公告)日：2006-07-06

申请号：JP2005226990

申请日：2005-08-04

Applicant: Fuji Electric Holdings Co Ltd ,  富士電機ホールディングス株式会社

Inventor： OKAMOTO KENJI

IPC: H01L23/14

CPC classification number: H05K1/053 ,  C23C4/02 ,  C23C24/04 ,  C23C28/321 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  H01L21/4867 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L25/072 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K2201/0179 ,  H05K2203/1344 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide an insulating substrate which is cheap by lessening a manday and is excellent in a heat dissipation nature and an insulation performance, and to provide a semiconductor device using such an insulating substrate. SOLUTION: An insulating substrate 1 comprises a metal base 2 used as a base substrate, an insulating layer 3 which is an ordinary temperature shock solidification film formed on this metal base 2 by an aerosol deposition method, and a circuit pattern portion 4 which is a sprayed coating formed on this insulating layer 3 by a cold spray method. Moreover, the semiconductor device loads this insulating substrate 1 and raises a heat dissipation characteristic. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过减小余量便宜并且散热性和绝缘性能优异的绝缘基板，并提供使用这种绝缘基板的半导体器件。 解决方案：绝缘基板1包括用作​​基底的金属基底2，通过气溶胶沉积法形成在该金属基底2上的常温冲击凝固膜的绝缘层3和电路图案部分4 其是通过冷喷涂法形成在该绝缘层3上的喷涂涂层。 此外，半导体器件负载该绝缘基板1并提高散热特性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006500783A

公开(公告)日：2006-01-05

申请号：JP2004540098

申请日：2003-09-15

Applicant: メドトロニック ミニメド インコーポレイテッド

Inventor： ラジヴ シャー ,  エドワード ジー バビラッキ ,  シャウン ペンド

IPC: H01L23/12 ,  H01L21/48 ,  H05K1/16 ,  H05K3/04 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L2924/0002 ,  H05K1/092 ,  H05K3/4061 ,  H05K3/4647 ,  H05K3/4667 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2203/0278 ,  H01L2924/00

Abstract: ベース基板（１２）と、互いに交互に配置される金属化層（１４）及び誘電体層（１６）と、から形成された多層基板デバイス。 各層は焼成なしで形成される。 ビア（４４）は例えば誘電体層（１６）のうち１層を通って延び、その誘電体層（１６）を覆う２個の金属化層（１４）を互いに接触させる。 ビア（４４）は、金属化層（１４）の頂面上にピラー（４０）を置き、金属化層（１４）の頂面上にピラー（４０）を取り巻くよう誘電体層（１６）を形成し、ピラー（４０）を除去することにより、形成できる。 誘電体層（１６）の次に他の誘電体層（１６）をまた金属化層（１４）の次に他の金属化層（１４）を設けることもできる。