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    Filter based on the combination via structures
    4.
    发明专利
    Filter based on the combination via structures 有权

    公开(公告)号：JP5354223B2

    公开(公告)日：2013-11-27

    申请号：JP2011527098

    申请日：2008-12-25

    Applicant: 日本電気株式会社

    Inventor： タラス クシュタ

    IPC: H01P7/04 ,  H01P1/205

    CPC classification number: H01P1/2056 ,  H01P1/203 ,  H01P7/04 ,  H01P7/08 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/09718

    Abstract: A filter is provided with a planar transmission line and a combined via structure connected to (both) one ends of the planar transmission line. The planar transmission line and the combined via structure are disposed in a same multilayer board. The combined via structure comprises two working parts. The first working part comprises a segment of signal via and a plurality of segments of ground vias surrounding the signal via. The second working part comprises a segment of the same signal via, a plurality of segments of the same ground vias, smooth conductive plate and corrugated conductive plate. The smooth conductive plate and the corrugated conductive plate are connected to the signal via. The second working part comprises a segment of the same signal via, a plurality of segments of the same ground vias and corrugated conductive plate. The corrugated conductive plate is connected to the signal via.

    A printed wiring board and a method of manufacturing the same
    5.
    发明专利
    A printed wiring board and a method of manufacturing the same 有权

    公开(公告)号：JP5326455B2

    公开(公告)日：2013-10-30

    申请号：JP2008239675

    申请日：2008-09-18

    Applicant: 日本電気株式会社

    Inventor： 和弘 柏倉

    IPC: H05K3/46

    CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/09718 ,  Y10T29/49124 ,  Y10T29/49155

    Abstract: A printed wiring board includes ground layers stacked via insulator(s), a first through hole, second through holes and signal wirings, each signal wiring extending from the first through hole through the clearance between predetermined ones of the ground layers, and disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring a layer in which the signal wiring is disposed has an outline such that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that the outline of second clearance does not contact with the second through holes.

    Multilayer printed wiring board
    9.
    发明专利
    Multilayer printed wiring board 有权
    空值

    公开(公告)号：JP5095398B2

    公开(公告)日：2012-12-12

    申请号：JP2007521326

    申请日：2006-06-14

    Applicant: イビデン株式会社

    Inventor： 隆 苅谷 ,  宏徳 田中

    IPC: H05K3/46

    CPC classification number: H05K1/18 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K7/00 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49133 ,  Y10T29/49162 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A multilayer printed wiring board 110 includes a mounting portion 160 on which a semiconductor device is mounted; and a layered capacitor portion 140 which includes a first layered electrode 141, a second layered electrode 142, and a ceramic high-dielectric layer 143 provided therebetween, and in which the first layered electrode 141 is connected to a ground line of the semiconductor device and the second layered electrode 142 is connected to a power supply line of the semiconductor device. The ratio of the number of via holes 161a, each of which constitutes a part of a conducting path that electrically connects a ground pad 161 to the ground line of a wiring pattern and which passes through the second layered electrode 141 in a non-contact manner, to the number of ground pads 161 is in the range of 0.05 to 0.7. The ratio of the number of second rod-shaped conductors 162b, each of which constitutes a part of a conducting path that electrically connects a power supply pad 162 to the power supply line of the wiring pattern and which passes through the first layered electrode 141 in a non-contact manner, to the number of power supply pad 162 is in the range of 0.05 to 0.7.

    Abstract translation: 多层印刷线路板110包括其上安装半导体器件的安装部分160; 以及分层电容器部分140，其包括设置在其间的第一层状电极141，第二层状电极142和陶瓷高电介质层143，并且其中第一层状电极141连接到半导体器件的接地线，以及 第二层状电极142连接到半导体器件的电源线。 通孔161a的数量构成导电路径的一部分的通孔161a的数量，该导通路径将接地焊盘161与布线图案的接地线电连接并且以非接触方式穿过第二层状电极141 ，接地焊盘161的数量在0.05〜0.7的范围内。 第二棒状导体162b的数量比构成将电源焊盘162电连接到布线图案的电源线并通过第一层叠电极141的导电路径的一部分 非接触方式与电源焊盘162的数量在0.05至0.7的范围内。

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