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12 条记录 (耗时 0.174 秒)

    Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process
    2.
    发明授权
    Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process 失效
    用于测量集成电路中的电介质层的平面度的集成电路和集成电路的工艺和结构，包括用于执行所述工艺的装置

    公开(公告)号：US5543633A

    公开(公告)日：1996-08-06

    申请号：US92717

    申请日：1993-07-15

    申请人： Aldo Losavio ,  Giuseppe Crisenza ,  Giorgio De Santi

    发明人： Aldo Losavio ,  Giuseppe Crisenza ,  Giorgio De Santi

    IPC分类号： G01B7/34 ,  G01B21/30 ,  H01L21/66 ,  H01L23/58

    CPC分类号： G01B21/30 ,  G01B7/345

    摘要： A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.

    摘要翻译： 一种用于测量集成电路中的平面度的方法包括：将待测量的电介质层平坦化地沉积在导电膜的预定测量路径上并测量所述测量路径的电阻。 这种测量路径的电阻在其沉积的表面是完全平坦的时是最小的，并且随着与完美平面性的表面偏差而增加。 描述了包含导电膜的测量部分和导电膜的参考部分的集成电路。

    Integrated electronic device having a low voltage electric supply
    4.
    发明申请
    Integrated electronic device having a low voltage electric supply 有权
    具有低电压电源的集成电子设备

    公开(公告)号：US20070019492A1

    公开(公告)日：2007-01-25

    申请号：US11401523

    申请日：2006-04-11

    申请人： Giovanni Campardo ,  Gian Vanalli ,  Pier Stoppino ,  Roberto Dossi ,  Aldo Losavio

    发明人： Giovanni Campardo ,  Gian Vanalli ,  Pier Stoppino ,  Roberto Dossi ,  Aldo Losavio

    IPC分类号： G11C5/14

    CPC分类号： G11C16/30

    摘要： A low supply voltage memory device includes a first supply pin and a second supply pin for the connection to a first supply voltage source (VDD) and to a second supply voltage source (VDDQ). The device may include a memory and at least one booster overlapped by way of a “system in package” system and in particular with “stacked-die” technology. This booster may be connected to the memory by way of a plurality of discrete components.

    摘要翻译： 低电源电压存储器件包括用于连接到第一电源电压源（VDD）和第二电源电压源（VDDQ）的第一电源引脚和第二电源引脚。 该装置可以包括存储器和至少一个通过“系统在封装”系统中重叠的增压器，特别是具有“堆叠式芯片”技术。 该升压器可以通过多个分立组件连接到存储器。

    Multi chip electronic system
    5.
    发明授权
    Multi chip electronic system 有权
    多芯片电子系统

    公开(公告)号：US08228684B2

    公开(公告)日：2012-07-24

    申请号：US12116852

    申请日：2008-05-07

    申请人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    发明人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    IPC分类号： H05K1/11 ,  H05K1/14

    CPC分类号： H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

    摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

    摘要翻译： 一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中 第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成 当第一和第二芯片叠加时相应的多个芯片间电连接。

    Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory device
    6.
    发明授权
    Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory device 有权
    具有擦除/编程故障的非易失性存储器件的自修复方法以及相对非易失性存储器件

    公开(公告)号：US06944072B2

    公开(公告)日：2005-09-13

    申请号：US10440043

    申请日：2003-05-15

    申请人： Rino Micheloni ,  Aldo Losavio

    发明人： Rino Micheloni ,  Aldo Losavio

    IPC分类号： G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44

    CPC分类号： G11C29/82 ,  G11C29/846

    摘要： The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in response to detecting an incorrect datum. Various solutions implement column, row and sector redundancy, both in case of erasing and programming.

    摘要翻译： 存储装置具有由多个标准扇区和冗余部分形成的存储块; 控制电路，其控制存储器单元的数据的编程和擦除; 以及用于存储在存储单元中的数据的正确性验证电路。 正确性验证电路由控制电路启用，并且在检测至少一个非功能单元的情况下产生不正确的基准信号。 此外，控制电路还激活冗余，使得能够响应于检测到不正确的数据而在冗余存储器级中存储冗余部分并存储冗余数据。 各种解决方案实现列，行和扇区冗余，无论在擦除和编程的情况下。

    Highly-planar interlayer dielectric thin films in integrated circuits
    7.
    发明授权
    Highly-planar interlayer dielectric thin films in integrated circuits 失效
    集成电路中的高平面层间绝缘薄膜

    公开(公告)号：US5598028A

    公开(公告)日：1997-01-28

    申请号：US468282

    申请日：1995-06-06

    申请人： Aldo Losavio ,  Maurizio Bacchetta

    发明人： Aldo Losavio ,  Maurizio Bacchetta

    IPC分类号： H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792 ,  H01L23/58 ,  H01L23/48

    CPC分类号： H01L21/76819 ,  H01L21/31051 ,  H01L2924/0002

    摘要： A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.

    摘要翻译： 用于制造集成电路中特别是非易失性半导体存储器件中的高平面层间电介质薄膜的平面化方法包括以下步骤：在半导体衬底上形成第一势垒层，其中先前获得了集成器件; 在第一未掺杂氧化物上形成含有磷和硼的第二氧化物层，硼的浓度低于磷的浓度; 在第二氧化物层上形成含有磷和硼的第三氧化物层，磷的浓度低于或等于硼的浓度; 在足以熔化第三氧化物层的温度下进行热处理，以获得平坦表面。

    MULTI CHIP ELECTRONIC SYSTEM
    9.
    发明申请
    MULTI CHIP ELECTRONIC SYSTEM 有权
    多芯片电子系统

    公开(公告)号：US20080278923A1

    公开(公告)日：2008-11-13

    申请号：US12116852

    申请日：2008-05-07

    申请人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    发明人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    IPC分类号： H05K1/14

    CPC分类号： H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

    摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

    摘要翻译： 一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中 第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成 当第一和第二芯片叠加时相应的多个芯片间电连接。

    Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device
    10.
    发明授权
    Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device 有权
    使用超安全架构的非易失性存储器件的自修复方法和非易失性存储器件

    公开(公告)号：US06922366B2

    公开(公告)日：2005-07-26

    申请号：US10423845

    申请日：2003-04-24

    申请人： Rino Micheloni ,  Aldo Losavio

    发明人： Rino Micheloni ,  Aldo Losavio

    IPC分类号： G11C29/00 ,  G11C16/04

    CPC分类号： G11C29/808

    摘要： A self-repair method intervenes at the end of an operation of modification of a nonvolatile memory, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array is divided into a basic portion, formed by a plurality of memory cells storing basic data, and into an in-the-field redundancy portion. The in-the-field redundancy portion is designed to store redundancy data that include a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a redundancy replacement circuit and a redundancy data verification circuit.

    摘要翻译： 在检测到仅一个非功能单元的情况下，在编程和擦除之间选择的非易失性存储器的修改操作结束时进行自修复方法，并且执行非功能单元的冗余。 为此，存储器阵列被分成由存储基本数据的多个存储单元形成的基本部分，并且被分割成现场冗余部分。 场内冗余部分被设计为存储包括不起作用的小区的正确内容，非功能小区的地址和激活的冗余标志的冗余数据。 冗余仅在应用预设的最大数量的修改脉冲之后被激活，并且使用冗余替换电路和冗余数据验证电路。