公开(公告)号：US20110124742A1

公开(公告)日：2011-05-26

申请号：US13018163

申请日：2011-01-31

Applicant: MENG-HWAN LEE ,  JUNG-WEI TSAI ,  YUN-YU CHEN ,  YING-CHIEH TSAI ,  CHUN-YING LIN

Inventor： MENG-HWAN LEE ,  JUNG-WEI TSAI ,  YUN-YU CHEN ,  YING-CHIEH TSAI ,  CHUN-YING LIN

IPC: A61K31/09 ,  A61P19/10 ,  A61P3/04 ,  A61P3/00

CPC classification number: A61K31/085 ,  A61K36/882

Abstract: The present invention is related to a composition and method of adipose cell differentiation inhibition.

Abstract translation: 本发明涉及脂肪细胞分化抑制的组成和方法。

公开(公告)号：US07932531B2

公开(公告)日：2011-04-26

申请号：US12506255

申请日：2009-07-21

Applicant: Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

Inventor： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

IPC: H01L33/00

CPC classification number: H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Abstract translation: 芯片封装包括热增强板，围绕热增强板接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

公开(公告)号：US07842550B2

公开(公告)日：2010-11-30

申请号：US12332362

申请日：2008-12-11

Applicant: Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

Inventor： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

IPC: H01L21/00

CPC classification number: H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract translation: 制造四边形扁平非引线封装的方法包括首先在牺牲层上形成图案化的导电层。 图案化导电层包括多个引线组。 许多芯片附着到牺牲层。 每个芯片都被其中一个引线组包围。 每个芯片电连接到一个引线组，并且在牺牲层上形成模制化合物以覆盖图案化的导电层和芯片。 然后将成型化合物和图案化导电层切割并切割，并且牺牲层被预切割以在牺牲层上形成多个凹部。 在模制化合物和图案化的导电层被切割并切割并且牺牲层被预切割之后，去除牺牲层。

公开(公告)号：US07790514B2

公开(公告)日：2010-09-07

申请号：US12270627

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/44

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.

Abstract translation: 提供了一种用于芯片封装结构的制造工艺。 首先，提供在图案化导电层上具有多个第一开口和第一图案化阻焊层的图案化导电层。 在图案化导电层上形成第二图案化阻焊层，使得第一图案化阻焊层和第二图案化阻焊层设置在图案化导电层的两个相对表面处。 芯片被结合到第一图案化阻焊层上，使得第一图案化阻焊层位于芯片和图案化导电层之间。 芯片通过穿过第一开口的多个接合线电连接到图案化的导电层。 形成至少一种模塑料，并且分离模塑料，第一图案化阻焊层和第二图案化阻焊层。

公开(公告)号：US07514106B2

公开(公告)日：2009-04-07

申请号：US11892630

申请日：2007-08-24

Applicant: Chia-Li Wei ,  Meng-Hwan Lee ,  Chun-Ying Lin ,  Jay Hua ,  Ying-Chieh Tsai

Inventor： Chia-Li Wei ,  Meng-Hwan Lee ,  Chun-Ying Lin ,  Jay Hua ,  Ying-Chieh Tsai

IPC: A01N65/00

CPC classification number: A61K36/45 ,  Y10S514/899

Abstract: A method for treating/relief of women's menstruation pain. The pain is reduced or relieved by externally administering an effective amount of an essential oil obtained from anthopogon.

Abstract translation: 治疗/缓解妇女月经痛的方法。 通过外用给予有效量的从anthopogon获得的精油减轻或减轻疼痛。

公开(公告)号：US20090064494A1

公开(公告)日：2009-03-12

申请号：US12270666

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H05K3/10

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer are between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供图案化导电层和图案化导电层上的图案化阻焊层。 多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和图案化的导电层之间。 芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。 形成至少一种模塑料以封装图案化的导电层，图案化的阻焊层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US08105876B2

公开(公告)日：2012-01-31

申请号：US13016453

申请日：2011-01-28

Applicant: Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

Inventor： Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

IPC: H01L21/00

CPC classification number: H01L21/4842 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K3/3426 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

公开(公告)号：US07902649B2

公开(公告)日：2011-03-08

申请号：US11934287

申请日：2007-11-02

Applicant: Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

Inventor： Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

IPC: H01L23/495

CPC classification number: H01L21/4842 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K3/3426 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract translation: 由无引线封装采用的引线框架包括多个封装单元和胶带。 每个封装单元具有带有多个开口的管芯焊盘和设置在多个开口中的多个销。 粘合带粘附到多个封装单元的表面并固定芯片焊盘和多个引脚。

公开(公告)号：US20100155929A1

公开(公告)日：2010-06-24

申请号：US12713333

申请日：2010-02-26

Applicant: Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

Inventor： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC: H01L25/065 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

公开(公告)号：US20100120201A1

公开(公告)日：2010-05-13

申请号：US12332362

申请日：2008-12-11

Applicant: Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

Inventor： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

IPC: H01L21/02

CPC classification number: H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract translation: 制造四边形扁平非引线封装的方法包括首先在牺牲层上形成图案化的导电层。 图案化导电层包括多个引线组。 许多芯片附着到牺牲层。 每个芯片都被其中一个引线组包围。 每个芯片电连接到一个引线组，并且在牺牲层上形成模制化合物以覆盖图案化的导电层和芯片。 然后将成型化合物和图案化导电层切割并切割，并且牺牲层被预切割以在牺牲层上形成多个凹部。 在模制化合物和图案化的导电层被切割并切割并且牺牲层被预切割之后，去除牺牲层。