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    Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device
    1.
    发明授权
    Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device 有权
    包括具有不同栅极结构的FinFET和半导体器件的制造方法的半导体器件

    公开(公告)号：US09564435B2

    公开(公告)日：2017-02-07

    申请号：US14754400

    申请日：2015-06-29

    Applicant: Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

    Inventor： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

    IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211

    Abstract: A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

    Abstract translation: 半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。 逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。 第一和第二栅极电介质层具有不同的厚度。 还讨论了相关设备和制造方法。

    METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS
    3.
    发明申请
    METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS 有权
    在PMOS / NMOS区域形成不同栅绝缘层的器件的方法

    公开(公告)号：US20080305620A1

    公开(公告)日：2008-12-11

    申请号：US12130646

    申请日：2008-05-30

    Applicant: Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

    Inventor： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

    IPC: H01L21/425

    CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

    Abstract: Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

    Abstract translation: 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

    Capacitor of semiconductor device and method of fabricating the same
    4.
    发明授权
    Capacitor of semiconductor device and method of fabricating the same 有权
    半导体器件的电容器及其制造方法

    公开(公告)号：US07442981B2

    公开(公告)日：2008-10-28

    申请号：US11316487

    申请日：2005-12-21

    Applicant: Gab-Jin Nam ,  Young-Sun Kim ,  Cha-Young Yoo ,  Jong-Cheol Lee ,  Jin-Tae Noh ,  Jae-Young Ahn ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo

    Inventor： Gab-Jin Nam ,  Young-Sun Kim ,  Cha-Young Yoo ,  Jong-Cheol Lee ,  Jin-Tae Noh ,  Jae-Young Ahn ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L28/75 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

    Abstract translation: 提供一种半导体器件的电容器及其制造方法。 在一个实施例中，电容器包括形成在半导体衬底上的下电极; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 上电极包括依次堆叠的第一导电层，第二导电层和第三导电层。 第一导电层包括金属层，导电金属氧化物层，导电金属氮化物层或导电金属氮氧化物层。 第二导电层包括掺杂多晶硅锗层。 第三导电层包括具有比第二导电层的电阻低的电阻的材料。

    Integrated circuit devices with metal-insulator-metal capacitors
    7.
    发明授权
    Integrated circuit devices with metal-insulator-metal capacitors 有权
    具有金属 - 绝缘体 - 金属电容器的集成电路器件

    公开(公告)号：US06992346B2

    公开(公告)日：2006-01-31

    申请号：US10807000

    申请日：2004-03-23

    Applicant: Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Jongwan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

    Inventor： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Jongwan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

    IPC: H01L29/096

    CPC classification number: H01L21/32051 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    Abstract: A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

    Abstract translation: 导电接触插塞延伸穿过电介质层中的开口以接触衬底并且包括延伸到邻近开口的电介质层上的加宽焊盘部分。 欧姆图案设置在插头的焊盘部分上，并且阻挡图案设置在欧姆图案上。 凹陷的第一电容器电极设置在阻挡图案上并且限定了远离基板的空腔。 电容器电介质层符合第一电容器电极的表面，并且第二电容器电极设置在与第一电容器电极相对的电容器电介质层上。 欧姆图案的侧壁，接触塞的阻挡图案和焊盘部分可以是基本上共面的，并且该器件还可以包括符合至少欧姆图案的侧壁，阻挡图案和焊盘部分的蚀刻停止层 接触插头。 描述相关的制造方法。

    Methods of manufacturing semiconductor devices having a recessed-channel
    8.
    发明授权
    Methods of manufacturing semiconductor devices having a recessed-channel 有权
    制造具有凹槽的半导体器件的方法

    公开(公告)号：US08119486B2

    公开(公告)日：2012-02-21

    申请号：US12984176

    申请日：2011-01-04

    Applicant: Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    Inventor： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    IPC: H01L21/336

    CPC classification number: H01L27/10876 ,  H01L29/66628

    Abstract: A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

    Abstract translation: 根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。 去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。 凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。 凹槽沟槽的底面的宽度小于其顶面的宽度。 有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。 第一区域的底面的面积增加。 第一区域的底面的深度减小。

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