Abstract:
This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.
Abstract:
A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.
Abstract:
A semiconductor apparatus includes a plurality of semiconductor chips which are stacked; and an auxiliary semiconductor chip configured to recover and transmit signals of the plurality of semiconductor chips through a plurality of through vias which extend vertically, at a predetermined time interval.
Abstract:
A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.
Abstract:
A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.
Abstract:
A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.
Abstract:
A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.
Abstract:
A method and apparatus for extracting advertisement keywords in association with situations of scenes of video include: establishing a knowledge database including a classification hierarchy for classifying situations of scenes of video and an advertisement keyword list, segmenting a video script corresponding to a received video in units of scenes, and determining a situation corresponding to each scene with reference to the knowledge database, and extracting an advertisement keyword corresponding to the situation of a scene of the received video with reference to the knowledge database.
Abstract:
The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.
Abstract:
A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.