Test circuit, memory system, and test method of memory system
    1.
    发明授权
    Test circuit, memory system, and test method of memory system 有权
    存储系统的测试电路,存储系统和测试方法

    公开(公告)号:US08918685B2

    公开(公告)日:2014-12-23

    申请号:US13603597

    申请日:2012-09-05

    CPC classification number: G11C29/56 G11C2029/5606

    Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.

    Abstract translation: 该技术涉及在减小测试电路的尺寸的同时平滑地对具有高存储容量的存储器电路进行测试。 根据本发明的测试电路包括被配置为对目标测试存储器电路进行测试的测试执行单元,被配置为存储用于测试执行单元的数据的内部存储单元,以及转换设置单元, 或作为用于存储测试执行单元的数据的外部存储单元的目标测试存储器电路的整个存储空间。

    Data line termination circuit
    2.
    发明授权
    Data line termination circuit 有权
    数据线终端电路

    公开(公告)号:US08330486B2

    公开(公告)日:2012-12-11

    申请号:US12956416

    申请日:2010-11-30

    CPC classification number: G11C7/1048 G11C11/4096 G11C11/4097

    Abstract: A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.

    Abstract translation: 数据线终端电路包括:摆动宽度检测单元,被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元,被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度,并且可以减小或增加数据线的电压的摆动宽度,以将数据线的电压保持在预定的 范围。

    SEMICONDUCTOR SYSTEM
    4.
    发明申请
    SEMICONDUCTOR SYSTEM 有权
    半导体系统

    公开(公告)号:US20120092062A1

    公开(公告)日:2012-04-19

    申请号:US13338716

    申请日:2011-12-28

    Abstract: A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.

    Abstract translation: 半导体系统包括控制器; 包括堆叠在所述控制器上的多个层叠半导体芯片的半导体器件以及被配置为共同地将信号传送到所述多个堆叠的半导体芯片的多个穿硅通孔(TSV) 以及缺陷信息传送TSV,被配置为将从半导体芯片中的至少一个依次输出的TSV缺陷信息传送到控制器,其中,所述控制器包括:多个第一修复熔丝单元,被配置为基于所述TSV缺陷信息来设置第一熔丝信息 ; 以及多个第一TSV选择单元,被配置为响应于所述第一熔丝信息选择性地驱动所述TSV。

    SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF 有权
    半导体存储器及其测试方法

    公开(公告)号:US20120057413A1

    公开(公告)日:2012-03-08

    申请号:US12948874

    申请日:2010-11-18

    CPC classification number: G11C7/22 G11C7/222 G11C29/006 G11C29/023

    Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

    Abstract translation: 一种半导体存储装置,包括:时钟控制单元,被配置为当使能信号被激活时接收第一时钟,并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元,被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元,被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US07973590B2

    公开(公告)日:2011-07-05

    申请号:US12615876

    申请日:2009-11-10

    Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

    Abstract translation: 半导体器件包括:第一传输线和布置在不同层的第二传输线; 与第一传输线和第二传输线耦合的接触熔丝; 功率驱动器,被配置为向所述接触保险丝施加电应力; 以及熔丝状态输出单元,被配置为输出具有与所述接触熔丝的电连接状态对应的逻辑电平的熔丝状态信号。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20110006391A1

    公开(公告)日:2011-01-13

    申请号:US12649452

    申请日:2009-12-30

    Abstract: A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.

    Abstract translation: 半导体器件包括多个堆叠的半导体芯片; 以及包括第一TSV和冗余TSV的多个穿硅通孔(TSV),并且被配置为共同地将信号传送到多个堆叠的半导体芯片。 半导体芯片中的至少一个包括多个修复熔丝单元,其被配置为存储关于TSV的至少一个缺陷的缺陷信息; 以及分配给各个TSV的多个锁存单元,并被配置为存储指示至少一个TSV缺陷并从多个修复熔丝单元输出的多个信号。

    On-chip data transmission control apparatus and method
    9.
    发明授权
    On-chip data transmission control apparatus and method 失效
    片上数据传输控制装置及方法

    公开(公告)号:US07516382B2

    公开(公告)日:2009-04-07

    申请号:US11292734

    申请日:2005-12-01

    CPC classification number: H04L25/4915

    Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

    Abstract translation: 片上数据传输控制器包括数据比较单元,用于将当前数据与先前数据进行比较,并且如果相转移的数据位数大于预设数量则发出反转标志;第一数据反转单元, 反转标志被激活并将反相数据提供到数据总线上的当前数据;以及第二数据反转单元,用于在反转标志被激活时反转经由数据总线发送的数据的相位并输出反相数据。 通过该控制器,通过减少通过GIO线输入的数据的转移次数,可以减少随着待发送的数据数量的增加而大幅度地发生的片上噪声,在使用多步预贴片结构来提高 存储器件的操作速度。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号:US20090046528A1

    公开(公告)日:2009-02-19

    申请号:US12018732

    申请日:2008-01-23

    Applicant: Hyung Dong Lee

    Inventor: Hyung Dong Lee

    Abstract: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

    Abstract translation: 半导体集成电路包括用于感测输入数据的读出放大器和用于在测试模式信号被激活时阻塞读出放大器与存储单元之间的信号路径的读出放大器控制器。

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