公开(公告)号：US08427196B2

公开(公告)日：2013-04-23

申请号：US12893848

申请日：2010-09-29

Applicant: Pierangelo Confalonieri ,  Federico Guanziroli ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Federico Guanziroli ,  Marco Zamprogno

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K17/162 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/66 ,  Y10T307/50

Abstract: A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state. The driving device connects the control terminal of the switch module to a third reference potential electrically distinct from the first and the second analog potentials, during each of the time intervals associated to the first or second driving transitions of the switch module.

Abstract translation: 系统包括提供第一和第二模拟电位的模拟电源电路。 开关模块基于驱动电信号，假设第一或第二状态来启用和禁止模拟电信号从源模块传送到用户模块。 驱动装置基于驱动电信号驱动开关模块的控制端子，允许开关模块呈现第一或第二状态。 驱动装置允许开关模块进行从第一状态到第二状态的第一驱动转变，以及从第二状态到第一状态的第二驱动转变。 在第二状态期间，驱动装置在第一状态期间交替地将控制端子连接到第一参考电位，并将第二参考电位交替地连接到第二参考电位。 在与开关模块的第一或第二驱动转换相关联的每个时间间隔期间，驱动装置将开关模块的控制端子连接到与第一和第二模拟电位电不同的第三参考电位。

公开(公告)号：US07888994B2

公开(公告)日：2011-02-15

申请号：US12395409

申请日：2009-02-27

Applicant: Marco Zamprogno ,  Pierangelo Confalonieri ,  Alberto Minuti

Inventor： Marco Zamprogno ,  Pierangelo Confalonieri ,  Alberto Minuti

IPC: G06G7/12 ,  G06G7/26

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit for conversion from differential to single-ended includes a differential amplifier stage and first and second buffer circuits. The differential amplifier stage includes a first and a second input; and a first and a different second charging circuit that can be operatively coupled, respectively, with an output of the conversion circuit and with an auxiliary output. Each of the first and second buffer circuits is functionally arranged between one of said outputs and between one of said charging circuits. The buffer circuits being configured so as to substantially equalize relative impedances seen towards said outputs.

Abstract translation: 用于从差分到单端转换的电路包括差分放大器级和第一和第二缓冲电路。 差分放大器级包括第一和第二输入; 以及可以分别与转换电路的输出和辅助输出可操作地耦合的第一和第二充电电路。 第一和第二缓冲电路中的每一个功能地布置在所述输出之一和所述充电电路之一之间。 缓冲电路被配置为基本上相等于所述输出端所看到的相对阻抗。

公开(公告)号：US07501974B2

公开(公告)日：2009-03-10

申请号：US11832946

申请日：2007-08-02

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M1/12

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.

Abstract translation: 用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。 分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。 逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。 转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。

公开(公告)号：US07158069B2

公开(公告)日：2007-01-02

申请号：US11097456

申请日：2005-04-01

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/462

Abstract: The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.

Abstract translation: 所描述的模拟数字转换器包括具有用于接收要转换的模拟量的输入的量化装置，具有用于提供与模拟量相对应的数字量的输出的寄存器，连接到量化装置的定时脉冲发生器和逻辑装置， 寄存器和定时脉冲发生器，并且能够通过激活量化装置来响应转换请求信号，以使得它们执行由定时脉冲定时的预定操作并将其加载到寄存器中以在 输出。 为了允许转换器即使在系统时钟不可用的情况下也能够运行，包含在转换器的其余部分的集成电路中的定时脉冲发生器包括能够被二进制数进行启动/停止的振荡器 施加到其激活输入的信号，并且逻辑装置能够产生振荡器的停止信号，并且包括用于产生要施加到振荡器的激活输入的二进制信号的装置。 该信号分别响应于转换请求信号和振荡器的停止信号而分别对应于振荡器的激活和去激活的第一或第二二进制状态。

公开(公告)号：US20140218096A1

公开(公告)日：2014-08-07

申请号：US14343099

申请日：2012-09-05

Applicant: Germano Nicollini ,  Marco Zamprogno

Inventor： Germano Nicollini ,  Marco Zamprogno

IPC: H03K17/687

CPC classification number: H03K17/6871 ,  H03F1/52 ,  H03F3/185 ,  H03F3/301

Abstract: An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a second mode by a digital data transmission stage 103 for digital data and supply, the audio output stage P-channel transistor MP being switchably back-gate biased by a bias circuit 107 according to the operating mode to achieve high-voltage tolerance.

Abstract translation: 具有CMOS音频输出级105的电子USB或类似装置101，用于在第一模式中，例如通过数字数据传输级103用于数字数据和供应的第二模式中通常使用的端口驱动头戴式耳机， 根据操作模式，音频输出级P沟道晶体管MP由偏置电路107可切换地逆栅偏置以实现高电压容限。

公开(公告)号：US20130314830A1

公开(公告)日：2013-11-28

申请号：US13990936

申请日：2011-12-02

Applicant: Marco Zamprogno ,  Alberto Minuti ,  Germano Nicollini

Inventor： Marco Zamprogno ,  Alberto Minuti ,  Germano Nicollini

IPC: H02H3/20

CPC classification number: H02H3/20 ,  H02H3/207 ,  H02J1/10 ,  H02J7/0031 ,  H02J7/345

Abstract: An apparatus (100) for protecting a circuit (200) from an input volume comprises a switchable element (10) arranged to couple the input voltage (VIN) to the circuit (200) in response to a first control signal (DRV1) having a first value and to decouple the input voltage (VIN) from the circuit (200) in response to the first control signal (DRV1) having a second value. A monitor stage (20) compares a monitored voltage (VMON) to a threshold (VIN). A controller (30) provides the first control signal (DRV1) to the switchable element (10), the first control signal (DRV1) having the first value when the monitored voltage (VMON) is on one side of the threshold (VTH), wherein the first value is independent of the input voltage (VIN) and the second value is equal to the input voltage (VIN).

Abstract translation: 一种用于保护电路（200）免受输入音量的装置（100）包括可转换元件（10），其被布置成响应于具有第一控制信号（DRV1）而将输入电压（VIN）耦合到电路（200） 并且响应于具有第二值的第一控制信号（DRV1），将输入电压（VIN）与电路（200）去耦。 监视级（20）将监测电压（VMON）与阈值（VIN）进行比较。 控制器（30）向所述可切换元件（10）提供所述第一控制信号（DRV1），当所述监视电压（VMON）位于所述阈值（VTH）的一侧时，所述第一控制信号（DRV1）具有所述第一值， 其中第一值与输入电压（VIN）无关，第二值等于输入电压（VIN）。

公开(公告)号：US07795947B2

公开(公告)日：2010-09-14

申请号：US12391574

申请日：2009-02-24

Applicant: Marco Zamprogno ,  Germano Nicollini ,  Alberto Minuti

Inventor： Marco Zamprogno ,  Germano Nicollini ,  Alberto Minuti

IPC: G06F7/64

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.

Abstract translation: 一种用于开关电容电路的集成缓冲装置，具有缓冲器，该缓冲器具有取决于可由缓冲装置提供的输入电压的输出电压的输出; 电容开关部件，其可以在第一和第二状态之间切换并分别连接到源极和缓冲器，以将输入电压传递到输出端; 所述电容开关元件设置有具有相关杂散电容的端子; 充电和放电装置，其被配置为在占用所述第二状态之前以参考电压对所述寄生电容进行预充电，并且在占用所述第一状态之前对所述杂散电容进行预放电。

公开(公告)号：US07675449B2

公开(公告)日：2010-03-09

申请号：US12172692

申请日：2008-07-14

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Riccardo Martignone

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Riccardo Martignone

IPC: H03M1/66

CPC classification number: H03M1/0648 ,  H03M1/687 ,  H03M1/747

Abstract: A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

Abstract translation: 一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关 用于将当前发生器连接到和从公共求和节点断开连接。 电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。 电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。

公开(公告)号：US20050195010A1

公开(公告)日：2005-09-08

申请号：US11055564

申请日：2005-02-09

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Federico Garibaldi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Federico Garibaldi

IPC: H03B1/00 ,  H03H11/26 ,  H03K5/00 ,  H03K5/04 ,  H03K5/13

CPC classification number: H03H11/26 ,  H03K5/04 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00123 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03K2005/00195

Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

Abstract translation: 时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。 电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得 具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。 电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。

公开(公告)号：US06897801B2

公开(公告)日：2005-05-24

申请号：US10483790

申请日：2002-06-13

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80 ,  H03M1/12 ,  G06F7/64 ,  G06G7/18 ,  G06G7/19

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

Abstract translation: 一种A / D转换器，具有电容器，其具有以二进制代码加权的采样电容器的第一阵列阵列，连接在第一公共电路节点和待充电的输入端子之间，所述第一公共电路节点和输入端子相对于要转换的信号的接地为输入电压， 然后根据SAR技术选择性地与两个差分参考端子连接，并且同时等效于第一和所有连接到第二节点的第二阵列的电容器选择性地连接到地和下差分电压端子。 两个节点连接到比较器的相应输入端。 逻辑单元根据预定的定时程序和作为比较器的输出的函数来控制两个阵列的电容器的连接。