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公开(公告)号：US20090296360A1
公开(公告)日：2009-12-03
申请号：US12131410
申请日：2008-06-02
CPC分类号： H05K7/1061 , H01L2224/16225 , H01L2224/73253 , H01L2924/15311 , H05K1/0231 , H05K1/0262 , H05K1/141 , H05K3/301 , H05K3/3436 , H05K2201/10325 , H05K2201/10409 , H05K2201/10545 , H05K2201/10598 , H05K2201/10734 , Y10T29/49144
摘要： A voltage regulator. The voltage regulator includes an interposer having, on a first side, a plurality of electrical connections suitable for coupling to a printed circuit board (PCB). The interposer also includes at least one power plane and at least one ground plane, wherein each of the power and ground planes is coupled to one or more of the electrical connections. The voltage regulator further includes a DC-DC converter that is electro-mechanically attachable to and detachable from the interposer. The interposer includes a socket, on a second side, that is suitable to receive two or more electro-mechanical connecting members of the DC-DC converter. When the DC-DC converter is attached to the interposer, at least one of the electromechanical connecting members is electrically coupled to a power plane of the interposer, while at least one other one of the electromechanical connecting members is electrically coupled to the ground plane.
摘要翻译： 电压调节器。 电压调节器包括插入器，其在第一侧具有适于耦合到印刷电路板（PCB）的多个电连接。 插入器还包括至少一个电源平面和至少一个接地平面，其中功率和接地平面中的每一个耦合到一个或多个电连接。 该电压调节器还包括一个DC-DC转换器，该DC-DC转换器可以机械地机械地连接到插入件上并从插入件上拆下。 插入器包括在第二侧上的适于接收DC-DC转换器的两个或更多个机电连接构件的插座。 当DC-DC转换器附接到插入器时，机电连接构件中的至少一个电耦合到插入器的功率平面，而机电连接构件中的至少一个电耦合到接地平面。
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公开(公告)号：US06965648B1
公开(公告)日：2005-11-15
申请号：US09565193
申请日：2000-05-04
IPC分类号： G01R31/3185 , G06F11/267 , H04L1/24 , H04L5/16 , H04L25/00
CPC分类号： G06F11/221 , G01R31/3185 , H04L1/242
摘要： A system may perform interconnect BIST (IBIST) testing on source synchronous links. The system may perform, at normal operating frequency, a source synchronous link test that tests a victim line on the source synchronous link using a transition weave pattern. The transition weave pattern causes interaction between a data transition on the victim line, previous transitions on the victim line, and transitions on the other lines of the link (the “aggressor” lines). The interaction caused may be: (i) a first crossing pulse on the victim line; (ii) a second crossing pulse of the opposite polarity on each aggressor line concurrent with the first crossing pulse on the victim line; and (iii) a reflection in the opposite direction of the first transition of the first crossing pulse, wherein the reflection results from a previous transition on the victim line.
摘要翻译： 系统可以在源同步链路上执行互连BIST（IBIST）测试。 该系统可以在正常操作频率下执行源同步链路测试，该测试使用转换编织模式测试源同步链路上的受害线路。 过渡组织模式导致受害者线上的数据转换，受害者线上的先前转换以及链接其他行（“侵略者”行）之间的转换之间的交互。 所造成的相互作用可能是：（i）受害线上的第一个交叉脉冲; （ii）与所述受害线上的第一交叉脉冲同时的每个侵略线上具有相反极性的第二交叉脉冲; 和（iii）在与第一交叉脉冲的第一跃迁相反的方向上的反射，其中反射来自在受害线上的先前转变。
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公开(公告)号：US08018738B2
公开(公告)日：2011-09-13
申请号：US12131410
申请日：2008-06-02
CPC分类号： H05K7/1061 , H01L2224/16225 , H01L2224/73253 , H01L2924/15311 , H05K1/0231 , H05K1/0262 , H05K1/141 , H05K3/301 , H05K3/3436 , H05K2201/10325 , H05K2201/10409 , H05K2201/10545 , H05K2201/10598 , H05K2201/10734 , Y10T29/49144
摘要： A voltage regulator. The voltage regulator includes an interposer having, on a first side, a plurality of electrical connections suitable for coupling to a printed circuit board (PCB). The interposer also includes at least one power plane and at least one ground plane, wherein each of the power and ground planes is coupled to one or more of the electrical connections. The voltage regulator further includes a DC-DC converter that is electro-mechanically attachable to and detachable from the interposer. The interposer includes a socket, on a second side, that is suitable to receive two or more electro-mechanical connecting members of the DC-DC converter. When the DC-DC converter is attached to the interposer, at least one of the electromechanical connecting members is electrically coupled to a power plane of the interposer, while at least one other one of the electromechanical connecting members is electrically coupled to the ground plane.
摘要翻译： 电压调节器。 电压调节器包括插入器，其在第一侧具有适于耦合到印刷电路板（PCB）的多个电连接。 插入器还包括至少一个电源平面和至少一个接地平面，其中功率和接地平面中的每一个耦合到一个或多个电连接。 该电压调节器还包括一个DC-DC转换器，该DC-DC转换器可以机械地机械地连接到插入件上并从插入件上拆下。 插入器包括在第二侧上的适于接收DC-DC转换器的两个或更多个机电连接构件的插座。 当DC-DC转换器附接到插入器时，机电连接构件中的至少一个电耦合到插入器的功率平面，而机电连接构件中的至少一个电耦合到接地平面。
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4.发明授权Method for assigning power and ground pins in array packages to enhance next level routing 有权在阵列封装中分配电源和接地引脚以提高下一级布线的方法公开(公告)号：US06521846B1
公开(公告)日：2003-02-18
申请号：US10041019
申请日：2002-01-07
IPC分类号： H05K116
CPC分类号： H05K1/112 , H01L23/49838 , H01L23/50 , H01L2224/16225 , H01L2924/01057 , H01L2924/01079 , H05K2201/09227 , H05K2201/10734 , Y10T29/49222
摘要： A method for assigning power and ground pins in array packages in order to enhance next level routing is provided. In one embodiment, the method comprises arranging connections of a semiconductor array package, the semiconductor package having an integrated circuit with power, ground, and signal connections, in 2×3 connection grids. Each connection grid includes a power connection and a ground connection which is adjacent to the power connection. The 2×3 connection grids are arranged so that each connection at the periphery is a signal connection. A 4:1:1 signal:power:ground connection ratio is maintained in the arrangement, wherein no more than four signal connections are present for each power connection, and no more than four signal connections are present for each ground connection.
摘要翻译： 提供了一种用于在阵列包中分配电源和接地引脚以便增强下一级路由的方法。 在一个实施例中，该方法包括在2x3连接网格中布置半导体阵列封装的连接，该半导体封装具有集成电路与电源，接地和信号连接。 每个连接电网包括电源连接和与电源连接相邻的接地连接。 2×3连接网格被布置成使得周边的每个连接是信号连接。 在该布置中维持4:1:1信号：电源：接地连接比，其中对于每个电力连接不存在不超过四个信号连接，并且对于每个接地连接不存在不超过四个信号连接。
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公开(公告)号：US06944692B2
公开(公告)日：2005-09-13
申请号：US09951928
申请日：2001-09-13
申请人： Brian L. Smith , Jue Wu , Jyh-Ming Jong , Wai Fong , Leo Yuan , Prabhansu Chakrabarti
发明人： Brian L. Smith , Jue Wu , Jyh-Ming Jong , Wai Fong , Leo Yuan , Prabhansu Chakrabarti
IPC分类号： H04L25/02 , G06F1/10 , G06F11/24 , G06F13/00 , G06F13/42 , G06K5/04 , H02H1/00 , H02H3/38 , H02H7/26 , H04L25/03 , G06F11/04
摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.
摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。
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6.发明授权Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection 有权源同步接收器链路初始化和输入浮点控制通过时钟检测和DLL锁定检测公开(公告)号：US06937680B2
公开(公告)日：2005-08-30
申请号：US09842332
申请日：2001-04-24
申请人： Wai Fong , Jyh-Ming Jong , Leo Yuan , Brian Smith , Prabhansu Chakrabarti
发明人： Wai Fong , Jyh-Ming Jong , Leo Yuan , Brian Smith , Prabhansu Chakrabarti
CPC分类号： H03L7/0812 , H03L7/095 , H04L7/0008
摘要： A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal. The method and apparatus may include a source synchronous receiver that is hot-swappable.
摘要翻译： 一种用于操作源同步接收机的方法和装置。 在一个实施例中，源同步接收器可以包括包括时钟检测器和时钟信号缓冲器的时钟接收器。 时钟检测器可以被配置为响应于检测到第一时钟信号而检测第一时钟信号并且断言时钟检测信号。 时钟缓冲器可以接收第一时钟信号并产生可以被驱动到数字锁相环（DLL）电路的第二时钟信号，其中第二时钟信号被再生并被驱动到源同步接收器的数据缓冲器。 时钟检测信号可以由时钟验证电路接收。 时钟验证电路可以被配置为在接收到时钟检测信号的失败时发起源同步接收器的复位。 源同步接收机的复位可以在本地执行，并且不重置其实现的设备的核心逻辑，也不会重置设备上的任何其他源同步端口。 因此，设备上的其他源同步端口以及核心逻辑可能能够正常地继续操作。 该方法和装置可以包括热插拔的源同步接收器。
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7.发明授权Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling 有权用于单端中心录音终端高速数字信号的预加重方案的方法和电路公开(公告)号：US06518792B2
公开(公告)日：2003-02-11
申请号：US09879501
申请日：2001-06-11
申请人： Jyh-Ming Jong , Prabhansu Chakrabarti , Leo Yuan
发明人： Jyh-Ming Jong , Prabhansu Chakrabarti , Leo Yuan
IPC分类号： H03K190175
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized. If the next logic signal has a logic value that is equivalent to either the first logic signal or the second logic signal, it may be transmitted without pre-emphasis.
摘要翻译： 一种预先强调传输逻辑信号的方法和电路。 该方法和电路可以应用于单端中心点终端I / O线。 在一个实施例中，驱动器电路可以被配置为监视由驱动器电路发送的信号的逻辑值（即逻辑0，逻辑1或逻辑低，逻辑高）。 驱动器电路可以将要发送的下一逻辑信号的逻辑值与先前发送的第一信号和第二先前发送的信号进行比较。 基于要发送的下一逻辑信号的逻辑值以及第一和第二逻辑信号的逻辑值，可能发生下一个逻辑信号的预加重。 如果第一和第二逻辑信号具有相同的逻辑值，并且下一逻辑信号具有不同的值，则可以预先强调下一个逻辑值。 如果下一个逻辑信号具有等同于第一逻辑信号或第二逻辑信号的逻辑值，则可以在没有预加重的情况下发送它。
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8.发明授权公开(公告)号：US07394260B2
公开(公告)日：2008-07-01
申请号：US11440383
申请日：2006-05-24
CPC分类号： G11C5/04
摘要： A method of tuning a test trace that is capacitively coupled to a number of signal traces. A method for determining a configuration of a device comprising signal traces and a capacitively coupled test trace may include selecting a test frequency of a test signal to be driven on selected signal traces during a test mode of device operation, and tuning circuit characteristics of the test trace to generate a bandpass frequency response including a passband and a stopband, where a detection frequency corresponding either to the test frequency or a selected harmonic of the test frequency is included in the passband. Tuning of circuit characteristics may include selecting a degree of capacitive coupling between the test trace and the signal traces such that, within a specified constraint for signal degradation on the signal traces, the bandpass frequency response of the given test trace satisfies a specified transmission requirement at the detection frequency.
摘要翻译： 调整与多个信号迹线电容耦合的测试迹线的方法。 用于确定包括信号迹线和电容耦合测试迹线的器件的配置的方法可以包括在器件操作的测试模式期间选择要在所选择的信号迹线上驱动的测试信号的测试频率，以及测试的调谐电路特性 跟踪以产生包括通带和阻带的带通频率响应，其中与测试频率相对应的检测频率或测试频率的选定谐波包括在通带中。 电路特性的调整可以包括选择测试迹线和信号迹线之间的电容耦合程度，使得在指定的约束条件下，信号迹线上的信号劣化，给定测试迹线的带通频率响应满足指定的传输要求 检测频率。
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9.发明申请公开(公告)号：US20070273386A1
公开(公告)日：2007-11-29
申请号：US11440383
申请日：2006-05-24
IPC分类号： G01R31/02
CPC分类号： G11C5/04
摘要： A method of tuning a test trace that is capacitively coupled to a number of signal traces. A method for determining a configuration of a device comprising signal traces and a capacitively coupled test trace may include selecting a test frequency of a test signal to be driven on selected signal traces during a test mode of device operation, and tuning circuit characteristics of the test trace to generate a bandpass frequency response including a passband and a stopband, where a detection frequency corresponding either to the test frequency or a selected harmonic of the test frequency is included in the passband. Tuning of circuit characteristics may include selecting a degree of capacitive coupling between the test trace and the signal traces such that, within a specified constraint for signal degradation on the signal traces, the bandpass frequency response of the given test trace satisfies a specified transmission requirement at the detection frequency.
摘要翻译： 调整与多个信号迹线电容耦合的测试迹线的方法。 用于确定包括信号迹线和电容耦合测试迹线的器件的配置的方法可以包括在器件操作的测试模式期间选择要在所选择的信号迹线上驱动的测试信号的测试频率，以及测试的调谐电路特性 跟踪以产生包括通带和阻带的带通频率响应，其中与测试频率相对应的检测频率或测试频率的选定谐波包括在通带中。 电路特性的调整可以包括选择测试迹线和信号迹线之间的电容耦合程度，使得在指定的约束条件下，信号迹线上的信号劣化，给定测试迹线的带通频率响应满足指定的传输要求 检测频率。
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公开(公告)号：US20060009931A1
公开(公告)日：2006-01-12
申请号：US11224277
申请日：2005-09-12
申请人： Brian Smith , Jue Wu , Jyh-Ming Jong , Wai Fong , Leo Yuan , Prabhansu Chakrabarti
发明人： Brian Smith , Jue Wu , Jyh-Ming Jong , Wai Fong , Leo Yuan , Prabhansu Chakrabarti
IPC分类号： G01R31/00
摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.
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