公开(公告)号：US06521846B1

公开(公告)日：2003-02-18

申请号：US10041019

申请日：2002-01-07

申请人： Michael C. Freda ,  Prabhansu Chakrabarti

发明人： Michael C. Freda ,  Prabhansu Chakrabarti

IPC分类号： H05K116

CPC分类号： H05K1/112 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01057 ,  H01L2924/01079 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y10T29/49222

摘要： A method for assigning power and ground pins in array packages in order to enhance next level routing is provided. In one embodiment, the method comprises arranging connections of a semiconductor array package, the semiconductor package having an integrated circuit with power, ground, and signal connections, in 2×3 connection grids. Each connection grid includes a power connection and a ground connection which is adjacent to the power connection. The 2×3 connection grids are arranged so that each connection at the periphery is a signal connection. A 4:1:1 signal:power:ground connection ratio is maintained in the arrangement, wherein no more than four signal connections are present for each power connection, and no more than four signal connections are present for each ground connection.

摘要翻译： 提供了一种用于在阵列包中分配电源和接地引脚以便增强下一级路由的方法。 在一个实施例中，该方法包括在2x3连接网格中布置半导体阵列封装的连接，该半导体封装具有集成电路与电源，接地和信号连接。 每个连接电网包括电源连接和与电源连接相邻的接地连接。 2×3连接网格被布置成使得周边的每个连接是信号连接。 在该布置中维持4:1:1信号：电源：接地连接比，其中对于每个电力连接不存在不超过四个信号连接，并且对于每个接地连接不存在不超过四个信号连接。

公开(公告)号：US07162795B2

公开(公告)日：2007-01-16

申请号：US10893507

申请日：2004-07-16

申请人： Larry D. Smith ,  Istvan Novak ,  Michael C. Freda

发明人： Larry D. Smith ,  Istvan Novak ,  Michael C. Freda

IPC分类号： H05K3/30

CPC分类号： H05K1/0231 ,  G06F1/26 ,  H05K1/0262 ,  H05K1/141 ,  H05K3/325 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09309 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144

摘要： A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

摘要翻译： 一种用于向集成电路分配电力的系统和方法。 在一个实施例中，功率层压板可以安装到印刷电路板（PCB）。 要分配功率的集成电路可以电耦合到PCB。 功率层压板可以包括一个或多个电源平面和一个或多个参考（即接地）平面，每对功率/参考平面由电介质层分开。 功率层压板还可以包括用于从外部电源接收功率的连接器或其它装置。 功率层压板可以电耦合到集成电路，从而使其能够向集成电路提供电力。 电力层压板还可以包括电压调节器电路和多个去耦电容器。

公开(公告)号：US07268302B1

公开(公告)日：2007-09-11

申请号：US11037709

申请日：2005-01-18

申请人： Lawrence D. Smith ,  Michael C. Freda

发明人： Lawrence D. Smith ,  Michael C. Freda

IPC分类号： H05K1/03

CPC分类号： H05K1/113 ,  H05K1/0231 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

摘要： A low inductance mount for decoupling capacitors. In one embodiment, a circuit carrier such as a printed circuit board (PCB) includes a surface layer, a first layer adjacent to the surface layer, and a second layer adjacent to the first layer. A conductive region is implemented on the surface layer, and is electrically coupled to a first circuit plane in the first layer. At least one mounting pad is located on the surface layer of the PCB within the conductive region. The mounting pad is electrically isolated from the remainder of the conductive region and is electrically coupled to a second circuit plane in the second layer. A capacitor is mounted on the PCB, wherein a first terminal of the capacitor is coupled to the conductive region and a second terminal is coupled to the mounting pad.

摘要翻译： 用于去耦电容器的低电感安装座。 在一个实施例中，诸如印刷电路板（PCB）的电路载体包括表面层，邻近表面层的第一层和与第一层相邻的第二层。 导电区域被实施在表面层上，并且电耦合到第一层中的第一电路平面。 至少一个安装垫位于导电区域内的PCB的表面层上。 安装焊盘与导电区域的其余部分电隔离，并且电耦合到第二层中的第二电路平面。 电容器安装在PCB上，其中电容器的第一端子耦合到导电区域，并且第二端子耦合到安装焊盘。

公开(公告)号：US06727780B2

公开(公告)日：2004-04-27

申请号：US10001781

申请日：2001-10-24

申请人： Istvan Novak ,  Valerie St.Cyr ,  Michael C. Freda ,  Merle Tetreault

发明人： Istvan Novak ,  Valerie St.Cyr ,  Michael C. Freda ,  Merle Tetreault

IPC分类号： H03H738

CPC分类号： H05K1/0234 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

摘要： A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

摘要翻译： 一种用于通过电耦合多个旁路电容器和在导体之间串联的对应的电阻元件来实现电力分配结构的导体之间的电阻抗的期望值的方法。 电阻元件可以是环形电阻器，并且可以向设计者提供对系统ESR的更大程度的控制。 环形电阻器可以包括第一端子，环形电阻器和第二端子。 第二端子可以位于环形电阻器的范围内。 环形电阻器可以印刷到导电平面（例如电源平面或接地平面）上，或者可以是分立的部件。

公开(公告)号：US06794581B2

公开(公告)日：2004-09-21

申请号：US09809837

申请日：2001-03-16

申请人： Larry D. Smith ,  Istvan Novak ,  Michael C. Freda ,  Ali Hassanzadeh

发明人： Larry D. Smith ,  Istvan Novak ,  Michael C. Freda ,  Ali Hassanzadeh

IPC分类号： H05K116

CPC分类号： H05K1/141 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01R12/52 ,  H05K1/0231 ,  H05K1/0263 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/09309 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126

摘要： A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The PCB may include a signal layer for conveying signals to and from the integrated circuit, but does not include any means for providing core power to the integrated circuit. Thus, all core power provided to the integrated circuit may be supplied by the power laminate.

摘要翻译： 一种用于向集成电路分配电力的系统和方法。 在一个实施例中，功率层压板可以安装到印刷电路板（PCB）。 要分配功率的集成电路可以电耦合到PCB。 功率层压板可以包括一个或多个电源平面和一个或多个参考（即接地）平面，每对功率/参考平面由电介质层分开。 功率层压板还可以包括用于从外部电源接收功率的连接器或其它装置。 功率层压板可以电耦合到集成电路，从而使其能够向集成电路提供电力。 PCB可以包括用于向集成电路传输信号的信号层，但不包括用于向集成电路提供核心功率的任何装置。 因此，提供给集成电路的所有核心功率可以由功率层叠体提供。

公开(公告)号：US06791846B2

公开(公告)日：2004-09-14

申请号：US09809826

申请日：2001-03-16

申请人： Larry D. Smith ,  Istvan Novak ,  Michael C. Freda

发明人： Larry D. Smith ,  Istvan Novak ,  Michael C. Freda

IPC分类号： H05K111

CPC分类号： H05K1/0231 ,  G06F1/26 ,  H05K1/0262 ,  H05K1/141 ,  H05K3/325 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09309 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144

摘要： A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

摘要翻译： 一种用于向集成电路分配电力的系统和方法。 在一个实施例中，功率层压板可以安装到印刷电路板（PCB）。 要分配功率的集成电路可以电耦合到PCB。 功率层压板可以包括一个或多个电源平面和一个或多个参考（即接地）平面，每对功率/参考平面由电介质层分开。 功率层压板还可以包括用于从外部电源接收功率的连接器或其它装置。 功率层压板可以电耦合到集成电路，从而使其能够向集成电路提供电力。 电力层压板还可以包括电压调节器电路和多个去耦电容器。

公开(公告)号：US08237058B2

公开(公告)日：2012-08-07

申请号：US12775349

申请日：2010-05-06

申请人： Michael C. Freda ,  Ricki D. Williams

发明人： Michael C. Freda ,  Ricki D. Williams

IPC分类号： H05K1/00

CPC分类号： H05K1/0248 ,  H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  Y10T29/49124

摘要： A printed circuit board (PCB) is configured to minimize skew between two parallel signal trace portions. The PCB comprises a laminate layer, which includes a fiberglass weave and includes a plastic resin deposited on each face of the fiberglass weave to form a first face and second face of the laminate layer. The fiberglass weave comprises a first set of fiberglass bundles in a first orientation interwoven with a second set of fiberglass bundles in a second orientation. Moreover, the PCB comprises trace a layer that is coupled to the first face of the laminate layer, and includes two or more signal traces. Two parallel trace portions of the two or more signal traces are configured to have a matching orientation and separation distance to a neighboring fiberglass bundle of the fiberglass weave, thereby ensuring that the two parallel trace portions encounter matching dielectric constants from the laminate layer.

摘要翻译： 印刷电路板（PCB）被配置为使两个并行信号迹线部分之间的偏移最小化。 PCB包括层压层，其包括玻璃纤维编织，并且包括沉积在玻璃纤维的每个表面上的塑料树脂，以形成层压层的第一面和第二面。 玻璃纤维编织包括第一组取向与第二组玻璃纤维束在第二方位交织的第一组玻璃纤维束。 此外，PCB包括迹线层，其耦合到层压层的第一面，并且包括两个或更多个信号迹线。 两个或更多个信号迹线的两个平行迹线部分被配置为具有与玻璃纤维编织相邻的玻璃纤维束的匹配取向和间隔距离，从而确保两个平行迹线部分遇到来自层压层的匹配的介电常数。

公开(公告)号：US20110272186A1

公开(公告)日：2011-11-10

申请号：US12775349

申请日：2010-05-06

申请人： Michael C. Freda ,  Ricki D. Williams

发明人： Michael C. Freda ,  Ricki D. Williams

IPC分类号： H05K1/00 ,  H05K3/10

CPC分类号： H05K1/0248 ,  H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  Y10T29/49124

摘要： A printed circuit board (PCB) is configured to minimize skew between two parallel signal trace portions. The PCB comprises a laminate layer, which includes a fiberglass weave and includes a plastic resin deposited on each face of the fiberglass weave to form a first face and second face of the laminate layer. The fiberglass weave comprises a first set of fiberglass bundles in a first orientation interwoven with a second set of fiberglass bundles in a second orientation. Moreover, the PCB comprises trace a layer that is coupled to the first face of the laminate layer, and includes two or more signal traces. Two parallel trace portions of the two or more signal traces are configured to have a matching orientation and separation distance to a neighboring fiberglass bundle of the fiberglass weave, thereby ensuring that the two parallel trace portions encounter matching dielectric constants from the laminate layer.

摘要翻译： 印刷电路板（PCB）被配置为使两个并行信号迹线部分之间的偏移最小化。 PCB包括层压层，其包括玻璃纤维编织，并且包括沉积在玻璃纤维的每个表面上的塑料树脂，以形成层压层的第一面和第二面。 玻璃纤维编织包括第一组取向与第二组玻璃纤维束在第二方位交织的第一组玻璃纤维束。 此外，PCB包括迹线层，其耦合到层压层的第一面，并且包括两个或更多个信号迹线。 两个或更多个信号迹线的两个平行迹线部分被配置为具有与玻璃纤维编织相邻的玻璃纤维束的匹配取向和间隔距离，从而确保两个平行迹线部分遇到来自层压层的匹配的介电常数。

公开(公告)号：US06760232B2

公开(公告)日：2004-07-06

申请号：US09809838

申请日：2001-03-16

申请人： Larry D. Smith ,  Michael C. Freda ,  Ali Hassanzadeh

发明人： Larry D. Smith ,  Michael C. Freda ,  Ali Hassanzadeh

IPC分类号： H05K702

CPC分类号： H05K1/141 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2924/15151 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0262 ,  H05K1/0263 ,  H05K3/3436 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/049 ,  H05K2201/09309 ,  H05K2201/10689 ,  H05K2201/10734

摘要： A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide core power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors. In one embodiment, the power laminate may include a plurality of apertures which allow for the passing of connections between the integrated circuit and the PCB. The integrated circuit may be mounted to the PCB by solder balls of a ball-grid array, elestomeric connections of a land-grid array, or other type of mounting. The each of the solder balls or elastomeric connections may pass though one of the apertures of the power laminate.

摘要翻译： 一种用于向集成电路分配电力的系统和方法。 在一个实施例中，功率层压板可以安装到印刷电路板（PCB）。 要分配功率的集成电路可以电耦合到PCB。 功率层压板可以包括一个或多个电源平面和一个或多个参考（即接地）平面，每对功率/参考平面由电介质层分开。 功率层压板还可以包括用于从外部电源接收功率的连接器或其它装置。 功率层压板可以电耦合到集成电路，从而使其能够向集成电路提供核心功率。 电力层压板还可以包括电压调节器电路和多个去耦电容器。 在一个实施例中，功率层压板可以包括允许集成电路和PCB之间的连接通过的多个孔。 该集成电路可以通过球栅阵列的焊球，陆格栅阵列的其他类型的安装的电子连接安装到PCB。 每个焊球或弹性体连接可以通过功率层叠体的一个孔。

公开(公告)号：US06534872B1

公开(公告)日：2003-03-18

申请号：US09371722

申请日：1999-08-10

申请人： Michael C. Freda ,  Han Y. Ko ,  Ali Hassanzadeh

发明人： Michael C. Freda ,  Han Y. Ko ,  Ali Hassanzadeh

IPC分类号： H01L2940

CPC分类号： H05K1/114 ,  H01L2924/15174 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09627 ,  H05K2201/10734

摘要： An apparatus and system comprising electrical interconnection devices (EIDs), such as printed wiring boards, semiconductor packages, and printed circuit boards, having novel via and signal trace positioning. The vias may be positioned off-center from the pattern of the surface pads. Via groups, or staircase vias, connect surface pads with vias extending into the electrical interconnection device. The via groups convert the pad geometry on the surface to a more open via pattern on one or more internal layers. The EID comprises a plurality of pads formed on a surface for providing electrical connections to another EID. A plurality of vias each extend from a corresponding pad to another layer of the printed wiring board. Each via is offset from a central location of its corresponding pad. A via group comprises a plurality of vias with a first via connecting a surface of the electrical interconnection device to a first inner layer electrically connects a pad on a surface of the electrical interconnection device to a second via. The second via extends from the first inner layer to a second layer of the electrical interconnection device. The centers of the first via and the second via are non-collinear. Another EID includes a uniformly spaced set of pads on the surface. Via groups, comprising a first set of vias and a second set of vias, extend from the uniformly spaced surface pads. Spacing among the second set of vias is non-uniform.

摘要翻译： 包括具有新颖的通孔和信号迹线定位的电互连装置（EID），例如印刷电路板，半导体封装和印刷电路板的装置和系统。 通孔可以离开表面焊盘的图案偏离中心。 通过组或楼梯通孔，将表面焊盘连接到延伸到电互连装置中的通孔。 通孔组将表面上的焊盘几何形状转换为一个或多个内部层上的更开放的通孔图案。 EID包括形成在表面上的多个焊盘，用于提供与另一EID的电连接。 多个通孔各自从相应的垫延伸到印刷线路板的另一层。 每个通孔偏离其对应的垫的中心位置。 通孔组包括多个通孔，第一通孔将电互连装置的表面连接到第一内层，将电互连装置的表面上的焊盘电连接到第二通孔。 第二通孔从电互连装置的第一内层延伸到第二层。 第一通孔和第二通孔的中心是非共线的。 另一个EID包括表面上均匀间隔的一组垫。 包括第一组通孔和第二组通孔的通孔组从均匀间隔的表面焊盘延伸。 第二组通道之间的间距是不均匀的。