公开(公告)号：US08026156B2

公开(公告)日：2011-09-27

申请号：US12489819

申请日：2009-06-23

Applicant: Soo Min Lee ,  Cheol Kyu Kim ,  Jaeun Yoo ,  Sung Hwan Jang ,  Masayoshi Koike

Inventor： Soo Min Lee ,  Cheol Kyu Kim ,  Jaeun Yoo ,  Sung Hwan Jang ,  Masayoshi Koike

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L33/0075 ,  H01L21/02002 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/0079

Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.

Abstract translation: 在制造氮化物类化合物层的方法中，首先制备GaN衬底。 在GaN衬底上形成具有预定图案的掩模层，以暴露GaN衬底的部分区域。 然后在部分曝光的GaN衬底上形成缓冲层。 缓冲层由具有10％以下与GaN的晶格失配的材料制成。 此后，氮化物类化合物从缓冲层的顶表面朝向掩模层的顶表面横向生长，并且氮化物基化合物层垂直生长至预定厚度。 此外，通过湿蚀刻除去掩模层和缓冲层，以将氮化物基化合物层与GaN衬底分离。

公开(公告)号：US20110186815A1

公开(公告)日：2011-08-04

申请号：US13083990

申请日：2011-04-11

Applicant: Soo Min LEE ,  Hee Seok Park ,  Jae Woong Han ,  Seong Suk Lee ,  Cheol Soo Sone

Inventor： Soo Min LEE ,  Hee Seok Park ,  Jae Woong Han ,  Seong Suk Lee ,  Cheol Soo Sone

IPC: H01L29/15

CPC classification number: H01L33/32 ,  B82Y10/00 ,  B82Y20/00 ,  H01L33/06

Abstract: There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately with each other, wherein the active layer includes a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer toward the p-type nitride semiconductor layer and having a quantum level higher than a quantum level of the first quantum well layer, and a tunneling quantum barrier layer formed between the first and second quantum well layers and having a thickness enabling a carrier to be tunneled therethrough.

Abstract translation: 提供了一种氮化物半导体器件，包括：n型氮化物半导体层; p型氮化物半导体层; 以及形成在所述n型和p型氮化物半导体层之间的有源层，所述有源层包括彼此交替沉积的多个量子阱层和至少一个量子势垒层，其中所述有源层包括第一量子阱 层，与第一量子阱层相邻形成朝向p型氮化物半导体层并且具有高于第一量子阱层的量子级的量子级的第二量子阱层，以及形成在第一量子阱层之间的隧穿量子势垒层 和第二量子阱层，并且具有能够使载体穿过其的厚度。

公开(公告)号：US07859086B2

公开(公告)日：2010-12-28

申请号：US11723065

申请日：2007-03-16

Applicant: Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

Inventor： Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

IPC: H01L33/00 ,  H01L29/04 ,  H01L29/12

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02664 ,  H01L33/0075

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 μm. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract translation: 氮化物半导体单晶衬底，其制造方法和使用其的垂直氮化物半导体器件的制造方法。 根据本发明的一个方面，在氮化物半导体单晶衬底中，沿着厚度方向分割上部和下部区域，所述氮化物单晶衬底的厚度至少为100μm。 这里，上部区域的掺杂浓度为下部区域的5倍以上。 优选地，上部区域中的基板的顶表面具有Ga极性。 此外，根据本发明的具体实施例，下部区域有意地未掺杂，并且上部区域是n掺杂的。 优选地，上部区域和下部区域中的每一个具有在厚度方向上基本相同的掺杂浓度。

公开(公告)号：US07459108B2

公开(公告)日：2008-12-02

申请号：US11338247

申请日：2006-01-24

Applicant: Kew-Ho Lee ,  In-Chul Kim ,  Soo-Min Lee ,  In-Hwan Choi

Inventor： Kew-Ho Lee ,  In-Chul Kim ,  Soo-Min Lee ,  In-Hwan Choi

IPC: B29C44/04 ,  B01D29/00 ,  B22F7/00 ,  B22F3/10

CPC classification number: B22F3/1103 ,  B01D67/0041 ,  B01D67/0058 ,  B01D71/022 ,  B01D2323/34 ,  B22F2998/10 ,  B22F2999/00 ,  C02F1/444 ,  Y10T428/169 ,  B22F1/0059 ,  B22F1/0085 ,  B22F2202/11

Abstract: The present invention relates to a method for preparing a metallic membrane, more particularly to a method for preparing metallic membranes, which comprises dissolving a transition metal of Period 3 and its alloy particle powder and synthetic polymer in a fixed ratio; radiating or casting to prepare a membrane precursor; oxidizing the synthetic polymer on the membrane precursor under a mixed gaseous atmosphere of nitrogen and hydrogen; and sintering the membrane precursor at a predetermined temperature. The metallic membrane prepared by the process of the present invention has excellent mechanical and chemical properties and enables to maintain a relatively small pore size and high porocity than traditional membranes. Therefore, it is useful for water treatment.

Abstract translation: 本发明涉及一种制备金属膜的方法，更具体地涉及一种制备金属膜的方法，其包括以固定比例溶解周期3的过渡金属及其合金颗粒粉末和合成聚合物; 辐射或铸造以制备膜前体; 在氮和氢的混合气体气氛下氧化膜前体上的合成聚合物; 并在预定温度下烧结膜前体。 通过本发明的方法制备的金属膜具有优异的机械和化学性质，并且能够保持比传统膜更小的孔径和高的孔隙率。 因此，它对于水处理是有用的。

公开(公告)号：US20070215983A1

公开(公告)日：2007-09-20

申请号：US11723065

申请日：2007-03-16

Applicant: Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

Inventor： Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

IPC: H01L29/12

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02664 ,  H01L33/0075

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 μm. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract translation: 氮化物半导体单晶衬底，其制造方法和使用其的垂直氮化物半导体器件的制造方法。 根据本发明的一个方面，在氮化物半导体单晶衬底中，沿厚度方向分割上下区域，氮化物单晶衬底的厚度至少为100μm。 这里，上部区域的掺杂浓度为下部区域的5倍以上。 优选地，上部区域中的基板的顶表面具有Ga极性。 此外，根据本发明的具体实施例，下部区域有意地未掺杂，并且上部区域是n掺杂的。 优选地，上部区域和下部区域中的每一个具有在厚度方向上基本相同的掺杂浓度。

公开(公告)号：US07067401B2

公开(公告)日：2006-06-27

申请号：US11235278

申请日：2005-09-27

Applicant: Sun Woon Kim ,  In Eung Kim ,  Hun Joo Hahm ,  Soo Min Lee ,  Dong Joon Kim ,  Je Won Kim

Inventor： Sun Woon Kim ,  In Eung Kim ,  Hun Joo Hahm ,  Soo Min Lee ,  Dong Joon Kim ,  Je Won Kim

IPC: H01L21/20

CPC classification number: C30B29/406 ,  C30B25/02 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/0262 ,  Y10S438/967

Abstract: Disclosed is a method of fabricating nitride semiconductors in a MOCVD reactor. GaN is first deposited on an inner wall of the MOCVD reactor, and a sapphire substrate is loaded into the MOCVD reactor. The sapphire substrate is heated and etching gas is injected into the MOCVD reactor. NH3 gas is injected into the MOCVD reactor to nitrify the surface of the sapphire substrate. A nitride semiconductor layer is grown on the nitrified sapphire substrate. By surface-reforming the sapphire substrate and then growing the nitride semiconductor layer on the surface-reformed sapphire substrate via MOCVD without formation of a low temperature buffer layer, an excellent nitride semiconductor structure can be realized. In this circumstance, the nitride semiconductor layer for example of GaN can be grown effectively on the surface-treated sapphire substrate because GaN deposition occurs on the sapphire substrate while it is etched.

公开(公告)号：US5981345A

公开(公告)日：1999-11-09

申请号：US891013

申请日：1997-07-10

Applicant: Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

Inventor： Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

IPC: H01L27/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L21/249

CPC classification number: H01L29/66477 ,  H01L29/1054 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66651

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

公开(公告)号：US5962879A

公开(公告)日：1999-10-05

申请号：US854665

申请日：1997-05-12

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L21/331 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract translation: 本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。 根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。 基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。 此外，不需要基底的选择性外延生长。 因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

公开(公告)号：US5897359A

公开(公告)日：1999-04-27

申请号：US987474

申请日：1997-12-09

Applicant: Deok Ho Cho ,  Soo Min Lee ,  Tae Hyeon Han ,  Byung Ryul Ryum ,  Kwang Eui Pyun

Inventor： Deok Ho Cho ,  Soo Min Lee ,  Tae Hyeon Han ,  Byung Ryul Ryum ,  Kwang Eui Pyun

IPC: H01L29/74 ,  H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: There is disclosed a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor having a good conformity and an improved speed characteristic, which includes the steps of sequentially laminating an underlying nitride film, an oxide film, a polycrystalline silicon film and an upper nitride on a semiconductor substrate on which devices are separated and a collector is formed; sequentially etching said upper nitride film and said polycrystalline silicon film using the emitter as a mask, and then forming a side wall nitride film; selectively wet-etching said oxide film to form a side base linker opening; burying said base linker opening with a polycrystalline silicon; oxidizing said polycrystalline silicon film buried into said base linker opening and then removing said oxide film by means of the selective wet-etch process; removing said upper nitride and then forming a silicon/silicon germanium film as a base film on the exposed thereof; and forming an emitter said silicon/silicon germanium film.

Abstract translation: 公开了一种制造具有良好一致性和改进的速度特性的硅/硅锗异质结双极晶体管的方法，其包括以下步骤：将下面的氮化物膜，氧化物膜，多晶硅膜和上部氮化物依次层压在 半导体衬底，器件分离并形成集电极; 使用发射极作为掩模，依次蚀刻所述上部氮化物膜和所述多晶硅膜，然后形成侧壁氮化物膜; 选择性地湿蚀刻所述氧化膜以形成侧基连接器开口; 用多晶硅掩埋所述基底连接器开口; 氧化所述多晶硅膜，所述多晶硅膜埋入所述基底连接器开口中，然后通过选择性湿蚀刻工艺除去所述氧化物膜; 去除所述上部氮化物，然后在其暴露时形成硅/硅锗膜作为基膜; 以及形成所述硅/硅锗膜的发射极。

公开(公告)号：US5459084A

公开(公告)日：1995-10-17

申请号：US358533

申请日：1994-12-19

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Oh-Joon Kwon

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Oh-Joon Kwon

IPC: H01L21/331 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG. thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.

Abstract translation: 公开了通过使用金属硅化物作为基底而使基极寄生电容完全降低的异质结双极晶体管的制造方法，包括以下步骤：在硅衬底中注入杂质以形成导电的埋地集电区; 在掩埋的集电极区上生长集电极外延层并形成场氧化物层; 选择性地将杂质注入到集电极外延层中以形成集电极沉降片; 在其上依次形成基底层和第一氧化物层; 图案化第一氧化物层以限定外部碱性区域; 使用图案化氧化物层作为掩模在外部基极区域中离子注入杂质并除去图案化的氧化物层; 在其上沉积金属硅化物膜以形成基极薄膜; 仅在基极薄膜上形成约500厚度的覆盖氧化物层; 在其上形成隔离氧化物层，并使用图案化的光掩模依次选择性地去除隔离氧化物层，封盖氧化物层，基极薄膜和基层，形成图案，隔离氧化物层被提供以电隔离基极和 发射器 在图案的两个侧边缘处形成侧壁氧化物层; 去除所述隔离氧化物层的一部分以限定发射极区域; 在其上形成钝化层并选择性地去除钝化层以形成接触孔; 以及在所述接触孔中沉积掺杂有杂质离子的多晶硅层以形成电极。