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公开(公告)号：US12288809B2
公开(公告)日：2025-04-29
申请号：US18612701
申请日：2024-03-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Miao-Syuan Fan , Pei-Wei Lee , Ching-Hua Lee , Jung-Wei Lee
IPC: H01L29/08 , H01L21/8234 , H01L27/088 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78
Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.
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公开(公告)号：US12287572B2
公开(公告)日：2025-04-29
申请号：US17232483
申请日：2021-04-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Cheng Hung Tsai , Sheng-Kang Yu , Shang-Chieh Chien , Heng-Hsin Liu , Li-Jui Chen
Abstract: A method includes: depositing a mask layer over a substrate; directing first radiation reflected from a central collector section of a sectional collector of a lithography system toward the mask layer according to a pattern; directing second radiation reflected from a peripheral collector section of the sectional collector toward the mask layer according to the pattern, wherein the peripheral collector section is vertically separated from the central collector section by a gap; forming openings in the mask layer by removing first regions of the mask layer exposed to the first radiation and second regions of the mask layer exposed to the second radiation; and removing material of a layer underlying the mask layer exposed by the openings.
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公开(公告)号：US20250133967A1
公开(公告)日：2025-04-24
申请号：US19001145
申请日：2024-12-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US20250133812A1
公开(公告)日：2025-04-24
申请号：US19002409
申请日：2024-12-26
Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.
Inventor： Meng-Che Tu , Wei-Chih Chen , Sih-Hao Liao , Yu-Hsiang Hu , Hung-Jui Kuo , Chen-Hua Yu
Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.
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公开(公告)号：US20250133778A1
公开(公告)日：2025-04-24
申请号：US18982482
申请日：2024-12-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Tse Hung , Chao-Ching Cheng , Tse-An Chen , Hung-Li Chiang , Tzu-Chiang Chen , Lain-Jong Li
Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.
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Patent Agency Ranking
公开(公告)号：US20250132150A1
公开(公告)日：2025-04-24
申请号：US18582070
申请日：2024-02-20
Applicant: Taiwan Semiconductor manufacturing Co., Ltd.
Inventor： Che Chi Shih , Chun-Yu Liu , James June Fan Hsu , Ku-Feng Yang , Szuya Liao
IPC: H01L21/02 , H01L21/324 , H01L29/66
Abstract: A method includes forming a first de-bond structure over a first substrate, where forming the first de-bond structure includes depositing a first de-bond layer over the first substrate, depositing a first silicon layer over the first de-bond layer, depositing a second de-bond layer over the first silicon layer, and depositing a second silicon layer over the second de-bond layer, epitaxially growing a first multi-layer stack over the first de-bond structure, bonding the first multi-layer stack to a second multi-layer stack, and performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.
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公开(公告)号：US20250132148A1
公开(公告)日：2025-04-24
申请号：US19001089
申请日：2024-12-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Hsi WANG , Yen-Yu CHEN
Abstract: A deposition system is provided capable of extending the chamber running time by preventing the target and other components from deformation due to thermal stress from the sputtering process by maintaining the temperature within the predetermined temperature range. The deposition system includes a substrate process chamber, a target within the substrate process chamber, and a plurality of grooves formed on the target in a circular formation. The plurality of grooves includes a first groove on a center portion of the target and a second groove on a periphery portion of the target.
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8.发明申请公开(公告)号：US20250130379A1
公开(公告)日：2025-04-24
申请号：US18961072
申请日：2024-11-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao CHEN , Hui-Yu LEE , Chung-Ming WENG , Jui-Feng KUAN , Chien-Te WU
Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.
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公开(公告)号：US12283590B2
公开(公告)日：2025-04-22
申请号：US18432543
申请日：2024-02-05
Inventor： Xin-Yong Wang , Li-Chun Tien , Chih-Liang Chen
IPC: H01L27/02 , H01L21/768 , H01L23/522
Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.
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公开(公告)号：US12283492B2
公开(公告)日：2025-04-22
申请号：US18401811
申请日：2024-01-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen
IPC: H01L23/00 , G02B6/122 , G02B6/136 , G02B6/30 , H01L21/56 , H01L23/31 , H01L23/522 , H01L23/528 , H01L23/538
Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
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