MIS contact structure with metal oxide conductor

    公开(公告)号:US10147798B2

    公开(公告)日:2018-12-04

    申请号:US15451164

    申请日:2017-03-06

    摘要: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR

    公开(公告)号:US20180083115A1

    公开(公告)日:2018-03-22

    申请号:US15451164

    申请日:2017-03-06

    摘要: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    SOI WAFERS AND DEVICES WITH BURIED STRESSOR
    6.
    发明申请

    公开(公告)号:US20200273991A1

    公开(公告)日:2020-08-27

    申请号:US16283578

    申请日:2019-02-22

    摘要: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.