公开(公告)号：US11424167B2

公开(公告)日：2022-08-23

申请号：US17067565

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Chih-Yi Huang ,  Keng-Tuan Chang

IPC: H01L21/56 ,  H01L21/66 ,  H01L25/00 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

公开(公告)号：US10074622B2

公开(公告)日：2018-09-11

申请号：US15425723

申请日：2017-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Lin Yeh ,  Jen-Chieh Kao ,  Chih-Yi Huang ,  Fu-Chen Chu

IPC: H01L23/49 ,  H01L43/02 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L43/02 ,  H01L2223/6605 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

公开(公告)号：US11855034B2

公开(公告)日：2023-12-26

申请号：US17334622

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hung Lai ,  Chin-Li Kao ,  Chih-Yi Huang ,  Teck-Chong Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16165 ,  H01L2224/16168 ,  H01L2224/73204 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

公开(公告)号：US11621220B2

公开(公告)日：2023-04-04

申请号：US17213006

申请日：2021-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Chih-Pin Hung ,  Teck-Chong Lee ,  Chih-Yi Huang

IPC: H01L23/02 ,  H01L23/498 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.

公开(公告)号：US11515249B2

公开(公告)日：2022-11-29

申请号：US17090671

申请日：2020-11-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Yi Huang ,  Chen-Chao Wang ,  Mi-Chun Hung

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.

公开(公告)号：US11901245B2

公开(公告)日：2024-02-13

申请号：US17893033

申请日：2022-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Chih-Yi Huang ,  Keng-Tuan Chang

IPC: H01L21/66 ,  H01L25/00 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/22 ,  H01L23/485 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

公开(公告)号：US11733294B2

公开(公告)日：2023-08-22

申请号：US16812232

申请日：2020-03-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Tsung-Tang Tsai ,  Chih-Yi Huang

IPC: H01L23/498 ,  G01R31/28 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: G01R31/2896 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L25/18 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/3192 ,  H01L2224/16227

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

公开(公告)号：US10886263B2

公开(公告)日：2021-01-05

申请号：US15721257

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： William T. Chen ,  John Richard Hunt ,  Chih-Pin Hung ,  Chen-Chao Wang ,  Chih-Yi Huang

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/13 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

公开(公告)号：US10522508B2

公开(公告)日：2019-12-31

申请号：US15968562

申请日：2018-05-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian Hu ,  Ming-Han Wang ,  Tsun-Lung Hsieh ,  Chih-Yi Huang ,  Chih-Pin Hung

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.

公开(公告)号：US12216157B2

公开(公告)日：2025-02-04

申请号：US18236930

申请日：2023-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Tsung-Tang Tsai ,  Chih-Yi Huang

IPC: H01L23/498 ,  G01R31/28 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.