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公开(公告)号：US20160104667A1
公开(公告)日：2016-04-14
申请号：US14971165
申请日：2015-12-16
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang
IPC: H01L23/498 , H01L21/027 , H01L21/48 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49811 , H01L21/0273 , H01L21/48 , H01L21/4846 , H01L21/4853 , H01L21/768 , H01L23/13 , H01L23/3135 , H01L23/3142 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13005 , H01L2224/13013 , H01L2224/13016 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/14131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
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公开(公告)号：US08884443B2
公开(公告)日：2014-11-11
申请号：US13895704
申请日：2013-05-16
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang
IPC: H01L21/48 , H01L23/48 , H01L23/00 , H01L21/768
CPC classification number: H01L23/49811 , H01L21/0273 , H01L21/48 , H01L21/4846 , H01L21/4853 , H01L21/768 , H01L23/13 , H01L23/3135 , H01L23/3142 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13005 , H01L2224/13013 , H01L2224/13016 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/14131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。
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公开(公告)号：US09437532B2
公开(公告)日：2016-09-06
申请号：US14971165
申请日：2015-12-16
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang
IPC: H01L23/498 , H01L23/48 , H01L21/48 , H01L21/768 , H01L23/00 , H05K3/40 , H01L21/027 , H01L23/31 , H01L23/13
CPC classification number: H01L23/49811 , H01L21/0273 , H01L21/48 , H01L21/4846 , H01L21/4853 , H01L21/768 , H01L23/13 , H01L23/3135 , H01L23/3142 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13005 , H01L2224/13013 , H01L2224/13016 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/14131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
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公开(公告)号：US20190148280A1
公开(公告)日：2019-05-16
申请号：US16247441
申请日：2019-01-14
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Chun-Che Lee , Ming-Chiang Lee , Yuan-Chang Su , Tien-Szu Chen , Chih-Cheng Lee , You-Lung Yen
IPC: H01L23/498 , H01L21/48 , H05K1/11 , H05K3/00
Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
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公开(公告)号：US10049976B2
公开(公告)日：2018-08-14
申请号：US15006306
申请日：2016-01-26
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang , Kuang-Hsiung Chen , Yu-Ying Lee
IPC: H01L23/498 , H01L21/48
Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.
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Patent Agency Ranking
公开(公告)号：US10181438B2
公开(公告)日：2019-01-15
申请号：US14523733
申请日：2014-10-24
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Chun-Che Lee , Ming-Chiang Lee , Yuan-Chang Su , Tien-Szu Chen , Chih-Cheng Lee , You-Lung Yen
Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
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公开(公告)号：US09224707B2
公开(公告)日：2015-12-29
申请号：US14509320
申请日：2014-10-08
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang
IPC: H01L23/00 , H01L23/48 , H01L21/48 , H01L21/768 , H01L23/498 , H05K3/40 , H01L23/13
CPC classification number: H01L23/49811 , H01L21/0273 , H01L21/48 , H01L21/4846 , H01L21/4853 , H01L21/768 , H01L23/13 , H01L23/3135 , H01L23/3142 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13005 , H01L2224/13013 , H01L2224/13016 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/14131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。
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公开(公告)号：US20150021766A1
公开(公告)日：2015-01-22
申请号：US14509320
申请日：2014-10-08
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang
IPC: H01L23/00
CPC classification number: H01L23/49811 , H01L21/0273 , H01L21/48 , H01L21/4846 , H01L21/4853 , H01L21/768 , H01L23/13 , H01L23/3135 , H01L23/3142 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13005 , H01L2224/13013 , H01L2224/13016 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/14131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。
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公开(公告)号：US09117697B2
公开(公告)日：2015-08-25
申请号：US14303371
申请日：2014-06-12
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Chun-Che Lee , Yuan-Chang Su , Wen-Chi Cheng , Guo-Cheng Liao , Yi-Chuan Ding
CPC classification number: H01L24/11 , H01L23/13 , H01L23/498 , H01L23/49827 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/11019 , H01L2224/11622 , H01L2224/1163 , H01L2224/13147 , H01L2224/14104 , H01L2224/16225 , H01L2924/12042 , H05K3/108 , H05K3/3436 , H05K3/4007 , H05K3/4682 , H05K2201/0376 , H05K2201/09045 , H05K2201/10674 , H05K2203/0723 , H05K2203/1461 , H01L2924/00
Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。
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公开(公告)号：US20140008814A1
公开(公告)日：2014-01-09
申请号：US13895704
申请日：2013-05-16
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Tien-Szu Chen , Chun-Che Lee , Sheng-Ming Wang
IPC: H01L23/48 , H01L21/768 , H01L21/48
CPC classification number: H01L23/49811 , H01L21/0273 , H01L21/48 , H01L21/4846 , H01L21/4853 , H01L21/768 , H01L23/13 , H01L23/3135 , H01L23/3142 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13005 , H01L2224/13013 , H01L2224/13016 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/14131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。
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