公开(公告)号：US20210020594A1

公开(公告)日：2021-01-21

申请号：US16512132

申请日：2019-07-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Tsung CHIU ,  Hui-Ying HSIEH ,  Hui Hua LEE ,  Cheng Yuan CHEN

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/56

Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.

公开(公告)号：US20180358276A1

公开(公告)日：2018-12-13

申请号：US16107887

申请日：2018-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Tsung CHIU ,  Meng-Jen WANG ,  Cheng-Hsi CHUANG ,  Hui-Ying HSIEH ,  Hui Hua LEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/786 ,  H01L23/13 ,  H01L23/14 ,  H01L23/29 ,  H01L23/492 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/07

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/78 ,  H01L21/786 ,  H01L23/13 ,  H01L23/14 ,  H01L23/142 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49861 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/97 ,  H01L25/074 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.

公开(公告)号：US20170148746A1

公开(公告)日：2017-05-25

申请号：US15250713

申请日：2016-08-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Tsung CHIU ,  Meng-Jen WANG ,  Cheng-Hsi CHUANG ,  Hui-Ying HSIEH ,  Hui Hua LEE

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/78 ,  H01L21/786 ,  H01L23/13 ,  H01L23/14 ,  H01L23/142 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49861 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/97 ,  H01L25/074 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth. A semiconductor die is disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface. The second surface of the semiconductor die is bonded to the bottom surface of the cavity. A distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.

公开(公告)号：US20220084914A1

公开(公告)日：2022-03-17

申请号：US17023267

申请日：2020-09-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Tsung CHIU ,  Hui-Ying HSIEH ,  Chun Hao CHIU ,  Chiuan-You DING

IPC: H01L23/495

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a lead frame and passive component. The lead frame includes a paddle and a plurality of leads. The lead frame includes a first surface and a second surface opposite to the first surface. The passive component includes an external connector. A pattern of the external connector is corresponding to a pattern of the plurality of leads of the lead frame.

公开(公告)号：US20210125911A1

公开(公告)日：2021-04-29

申请号：US16664631

申请日：2019-10-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Tsung CHIU ,  Hui-Ying HSIEH ,  Kuo-Hua CHEN ,  Cheng Yuan CHEN

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/768

Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

公开(公告)号：US20190122969A1

公开(公告)日：2019-04-25

申请号：US16156991

申请日：2018-10-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hui Hua LEE ,  Hui-Ying HSIEH ,  Cheng-Hung KO ,  Chi-Tsung CHIU

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.

公开(公告)号：US20140011325A1

公开(公告)日：2014-01-09

申请号：US14016850

申请日：2013-09-03

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Shin-Hua CHAO ,  Chao-Yuan LIU ,  Hui-Ying HSIEH ,  Chih-Ming CHUNG

IPC: H01L23/00

CPC classification number: H01L24/96 ,  H01L21/56 ,  H01L23/145 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括衬底，半导体元件，封装体和导电部件。 基板具有电接触。 半导体元件设置在基板上。 封装体覆盖半导体元件并且限定了电触头暴露的通孔。 其中，包装体包括树脂体和多个纤维层。 纤维层设置在树脂体中并限定多个布置成阵列的纤维孔。 导电部件通过通孔与基板电连接。