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    Shadow ram cell having a shallow trench eeprom
    2.
    发明授权
    Shadow ram cell having a shallow trench eeprom 失效
    阴影柱塞细胞具有浅沟eeprom

    公开(公告)号：US5196722A

    公开(公告)日：1993-03-23

    申请号：US848913

    申请日：1992-03-12

    申请人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    发明人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/788

    CPC分类号： H01L27/10829 ,  H01L27/105 ,  H01L29/7881

    摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

    摘要翻译： 公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。 浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。 本发明的阵列提供高密度影子RAM。 还公开了用于制造本发明的装置的方法。

    Sidewall strap
    3.
    发明授权
    Sidewall strap 失效
    侧壁带

    公开(公告)号：US5521118A

    公开(公告)日：1996-05-28

    申请号：US440574

    申请日：1995-05-15

    申请人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

    发明人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

    CPC分类号： H01L27/10861 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

    摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

    摘要翻译： 本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。 侧壁连接器具有包括外表面的顶部部分。 导电构件接触顶部，将轨道连接到导电区域或外部导体。 位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。 然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。 通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。 连接器用于形成用于DRAM单元的带子。

    Vertical precharge structure for DRAM
    5.
    发明授权
    Vertical precharge structure for DRAM 失效
    DRAM的垂直预充电结构

    公开(公告)号：US5684313A

    公开(公告)日：1997-11-04

    申请号：US603832

    申请日：1996-02-20

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/108

    摘要： A DRAM one device cell and an associated precharge circuit are integrated together in a novel structure having an area of only four square features. The structure also provides physical and electrical separation between adjacent cells along a direction parallel to the DRAM word lines. The DRAM bit line length per bit is reduced by 50% relative to a conventional planar integrated structure disclosed elsewhere. As a result, bit line capacitance is also substantially reduced, and the effectiveness of a precharge technique for reduction of DRAM power consumption is enhanced by the dense novel structure.

    摘要翻译： DRAM一个器件单元和相关联的预充电电路以仅具有四个正方形特征的区域的新颖结构集成在一起。 该结构还沿着与DRAM字线平行的方向在相邻单元之间提供物理和电气分离。 相对于其他地方公开的常规平面集成结构，每位的DRAM位线长度减小了50％。 结果，位线电容也显着降低，并且通过密集的新颖结构增强了用于减少DRAM功耗的预充电技术的有效性。

    Self-aligned buried strap for trench type DRAM cells
    6.
    发明授权
    Self-aligned buried strap for trench type DRAM cells 失效
    用于沟槽型DRAM单元的自对准埋地带

    公开(公告)号：US5360758A

    公开(公告)日：1994-11-01

    申请号：US161823

    申请日：1993-12-03

    申请人： Gary B. Bronner ,  John K. DeBrosse ,  Donald M. Kenney

    发明人： Gary B. Bronner ,  John K. DeBrosse ,  Donald M. Kenney

    IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10829

    摘要： A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

    摘要翻译： 具有浅沟槽隔离的深沟槽型DRAM单元具有掩埋多晶硅带，其被限定为不使用单独的掩模，通过在浅沟槽清晰度之前在至少深沟槽上沉积带材料并且使用浅沟槽隔离掩模部分地重叠 深沟槽，从而在切割浅沟槽的过程中限定带子。

    Method of making a high density V-MOS memory array
    8.
    发明授权
    Method of making a high density V-MOS memory array 失效
    制造高密度V-MOS存储器阵列的方法

    公开(公告)号：US4326332A

    公开(公告)日：1982-04-27

    申请号：US173508

    申请日：1980-07-28

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/10 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/74 ,  H01L29/749 ,  H01L29/78 ,  H01L21/265 ,  H01L21/308

    CPC分类号： H01L27/10876 ,  H01L21/30608 ,  H01L21/76877 ,  H01L27/10823 ,  Y10S438/901

    摘要： A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin regions with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having self-aligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of V-grooves. A method of eliminating the overhang of a masking layer after anisotropic etching includes the oxidation of the V-groove followed by etching to remove both the grown oxide and the overhang is also disclosed.

    摘要翻译： 一种用于提供高密度动态存储单元的方法，其通过使用具有多个平行的厚和薄区域的器件限定掩模层来提供两个V-MOSFET器件元件及其互连的自对准。 使用限定垂直于掩模层中的区域排列的多个平行区域的蚀刻掩模，在薄区域的部分中蚀刻孔。 在孔中形成具有自对准栅电极的V-MOSFET器件，并且在薄区的其余部分之下形成器件互连线。 可以使用各向异性蚀刻和方向依赖蚀刻的组合，例如反应离子蚀刻来延长V形槽的深度。 还公开了在各向异性蚀刻之后消除掩模层的突出部的方法，包括V型槽的氧化，然后进行蚀刻以去除生长的氧化物和悬垂两者。

    Trench capacitor precharge structure and leakage shield
    9.
    发明授权
    Trench capacitor precharge structure and leakage shield 失效
    沟槽电容器预充电结构和漏电屏蔽

    公开(公告)号：US5684314A

    公开(公告)日：1997-11-04

    申请号：US617138

    申请日：1996-03-18

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/108

    摘要： An integrated structure is provided that includes a DRAM cell with a trench storage capacitor, and a corresponding storage node precharge circuit. The entire structure ideally requires only eight square features of area per memory bit. The structure also provides a partial leakage current shield for the DRAM storage node diffusion, thereby improving the data hold time. A graded impurity region around the storage node diffusion enhances the leakage shielding effect. The structure can be operated independently as a DRAM leakage shield if the precharge circuit is not needed. In that case, a junction diffusion in the structure can be eliminated and a leakage shielding effect is still achieved.

    摘要翻译： 提供了一种集成结构，其包括具有沟槽存储电容器的DRAM单元和相应的存储节点预充电电路。 整个结构理想地仅需要每个存储器位的八个方形特征的面积。 该结构还为DRAM存储节点扩散提供了部分泄漏电流屏蔽，从而提高了数据保持时间。 存储节点扩散周围的渐变杂质区域增强了漏电屏蔽效应。 如果不需要预充电电路，则该结构可以独立地作为DRAM漏电屏蔽来操作。 在这种情况下，可以消除结构中的结扩散，并且仍然实现泄漏屏蔽效果。

    Porous silicon trench and capacitor structures
    10.
    发明授权
    Porous silicon trench and capacitor structures 失效
    多孔硅沟槽和电容器结构

    公开(公告)号：US5635419A

    公开(公告)日：1997-06-03

    申请号：US435028

    申请日：1995-05-04

    申请人： Peter J. Geiss ,  Donald M. Kenney

    发明人： Peter J. Geiss ,  Donald M. Kenney

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10861 ,  H01L28/82 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/96 ,  Y10S977/721 ,  Y10S977/888 ,  Y10S977/899

    摘要： The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalls thereof. Such a trench can then be utilized to form a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.

    摘要翻译： 本发明提供了利用多孔硅作为电容器结构的第一板的电容器结构，从而大大增加了可用于电容器的表面积，从而可以获得电容。 本发明还提供了一种沟槽结构，其具有围绕其侧壁的多孔硅区域。 然后可以利用这种沟槽来形成根据本发明的电容器。 还提供了根据本发明的制造电容器和沟槽结构的方法。 使用电解阳极蚀刻制造多孔硅。