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    FCVD LINE BENDING RESOLUTION BY DEPOSITION MODULATION
    2.
    发明申请
    FCVD LINE BENDING RESOLUTION BY DEPOSITION MODULATION 有权
    FCVD线弯曲分辨率由沉积物调制

    公开(公告)号：US20160181089A1

    公开(公告)日：2016-06-23

    申请号：US14954634

    申请日：2015-11-30

    Applicant: Applied Materials, Inc.

    Inventor： Jingmei LIANG ,  Kiran V. THADANI ,  Jessica S. KACHIAN ,  Nagarajan RAJAGOPALAN

    IPC: H01L21/02

    CPC classification number: B81B3/00 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/505 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02315

    Abstract: A method of reducing line bending and surface roughness of a substrate with pillars includes forming a treated surface by treating a pillar-containing substrate with a radical. The radical may be silicon-based, nitrogen-based or oxygen-based. The method may include forming a dielectric film over the treated surface by reacting an organosilicon precursor and an oxygen precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. A method of reducing line bending and surface roughness of a substrate with pillars includes forming a dielectric film over a pillar-containing substrate by reacting an organosilicon precursor, an oxygen precursor, and a radical precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. The radical precursor may be selected from the group consisting of nitrogen-based radical precursor, oxygen-based radical precursor, and silicon-based radical precursor.

    Abstract translation: 减少具有柱的基体的线弯曲和表面粗糙度的方法包括通过用基团处理含柱基底来形成处理表面。 该基团可以是硅基，氮基或氧基。 该方法可以包括通过使有机硅前体和氧前体反应而在处理过的表面上形成电介质膜。 该方法可以包括在约150℃或更低的温度下固化电介质膜。 减少具有柱的基板的线弯曲和表面粗糙度的方法包括通过使有机硅前体，氧前体和自由基前体反应形成在含柱底物上的电介质膜。 该方法可以包括在约150℃或更低的温度下固化电介质膜。 自由基前体可以选自氮基自由基前体，氧基自由基前体和硅基自由基前体。

    GATE STACK MATERIALS FOR SEMICONDUCTOR APPLICATIONS FOR LITHOGRAPHIC OVERLAY IMPROVEMENT
    6.
    发明申请
    GATE STACK MATERIALS FOR SEMICONDUCTOR APPLICATIONS FOR LITHOGRAPHIC OVERLAY IMPROVEMENT 有权
    用于层间叠加改进的半导体应用的栅极堆叠材料

    公开(公告)号：US20160203971A1

    公开(公告)日：2016-07-14

    申请号：US14879043

    申请日：2015-10-08

    Applicant: Applied Materials, Inc.

    Inventor： Michael TSIANG ,  Praket P. JHA ,  Xinhai HAN ,  Nagarajan RAJAGOPALAN ,  Bok Hoen KIM ,  Tsutomu KIYOHARA ,  Subbalakshmi SREEKALA

    IPC: H01L21/02 ,  H01L27/115

    CPC classification number: H01L21/0217 ,  H01L21/02274 ,  H01L27/11582

    Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

    Abstract translation: 本公开的实施例提供了在半导体衬底上制造具有最小光刻重叠误差的膜层的方法和系统。 在一个实施例中，用于在衬底上形成膜层的方法包括将包含含硅气体和反应气体的沉积气体混合物供给到设置在处理室中的衬底支撑体上的衬底上，在存在 在处理室中沉积气体混合物，将电流施加到设置在处理室中的等离子体轮廓调制器，同时将沉积气体混合物供应到处理室中，并且在衬底上沉积膜层的同时旋转衬底。

    DIELECTRIC-METAL STACK FOR 3D FLASH MEMORY APPLICATION
    7.
    发明申请
    DIELECTRIC-METAL STACK FOR 3D FLASH MEMORY APPLICATION 审中-公开

    公开(公告)号：US20180247808A1

    公开(公告)日：2018-08-30

    申请号：US15959646

    申请日：2018-04-23

    Applicant: Applied Materials, Inc.

    Inventor： Xinhai HAN ,  Nagarajan RAJAGOPALAN ,  Sung Hyun HONG ,  Bok Hoen KIM ,  Mukund SRINIVASAN

    IPC: H01L21/02 ,  H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L21/02274 ,  H01L21/02164 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A method is provided for forming a stack of film layers for use in 3D memory devices. The method starts with providing a substrate in a processing chamber of a deposition reactor. Then one or more process gases suitable for forming a dielectric layer are supplied into the processing chamber of the deposition reactor forming a dielectric layer on the substrate. Then one or more process gases suitable for forming a metallic layer are supplied into the processing chamber of the deposition reactor forming a metallic layer on the dielectric layer. Then one or more process gases suitable for forming a metallic nitride adhesion layer are supplied into the processing chamber of the deposition reactor forming a metallic nitride adhesion layer on the metallic layer. The sequence is then repeated to form a desired number of layers.

    HIGH THROUGHPUT MULTI-LAYER STACK DEPOSITION
    9.
    发明申请
    HIGH THROUGHPUT MULTI-LAYER STACK DEPOSITION 审中-公开
    高通量多层堆积沉积

    公开(公告)号：US20140287593A1

    公开(公告)日：2014-09-25

    申请号：US14218103

    申请日：2014-03-18

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Xinhai HAN ,  Zhijun JIANG ,  Nagarajan RAJAGOPALAN ,  Bok Hoen KIM ,  Ramprakash SANKARAKRISHNAN ,  Ganesh BALASUBRAMANIAN ,  Juan Carlos ROCHA- ALVAREZ ,  Mukund SRINIVASAN

    IPC: H01L21/02

    CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/509 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022

    Abstract: Methods and apparatus for high rate formation of multi-layer stacks on semiconductor substrate is provided. A chamber for forming such stacks at high rates includes a first precursor line and a second precursor line. The first precursor line is coupled to a first diverter, which is coupled to a gas inlet in a lid assembly of the chamber. The second precursor line is coupled to a second diverter, which is also coupled to the gas inlet. The first diverter is also coupled to a first divert line, and the second diverter is coupled to a second divert line. Each of the first and second divert lines is coupled to a divert exhaust system. A chamber exhaust system is coupled to the chamber. The diverters are typically located close to the lid assembly.

    Abstract translation: 提供了在半导体衬底上高速形成多层叠层的方法和装置。 用于以高速率形成这种堆叠的室包括第一前体管线和第二前体管线。 第一前体管线耦合到第一分流器，其连接到腔室的盖组件中的气体入口。 第二前体管线连接到第二转向器，第二分配器也联接到气体入口。 第一分流器还耦合到第一转向管线，并且第二分流器联接到第二转向管线。 第一和第二转向管线中的每一个联接到转向排气系统。 腔室排气系统联接到腔室。 分流器通常位于盖组件附近。

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