公开(公告)号：US08082055B2

公开(公告)日：2011-12-20

申请号：US12499345

申请日：2009-07-08

申请人： Chun-Hsien Lin ,  Andy Tsen ,  Jui-Long Chen ,  Sunny Wu ,  Jong-I Mou ,  Chia-Hung Huang

发明人： Chun-Hsien Lin ,  Andy Tsen ,  Jui-Long Chen ,  Sunny Wu ,  Jong-I Mou ,  Chia-Hung Huang

IPC分类号： G06F19/00

CPC分类号： G06Q10/06 ,  G06Q30/0202

摘要： A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

摘要翻译： 公开了一种用于在集成电路器件制造工艺的早期阶段提供容量比预测的方法。 该方法包括从一个或多个处理的晶片批次收集历史数据; 从一个或多个偏斜晶片批量收集测量数据; 从收集的历史数据和收集的测量数据生成估计的基线分布; 基于一个或多个指定参数和所生成的估计基线分布产生估计的性能分布; 通过对所生成的估计性能分布应用仓定义和产量退化因子估计来确定仓比预测; 根据仓比预测确定一个或多个生产目标; 以及基于所述一个或多个确定的生产目标来处理一个或多个晶圆。

公开(公告)号：US20110010215A1

公开(公告)日：2011-01-13

申请号：US12499345

申请日：2009-07-08

申请人： Chun-Hsien Lin ,  Andy Tsen ,  Jui-Long Chen ,  Sunny Wu ,  Jong-I Mou ,  Chia-Hung Huang

发明人： Chun-Hsien Lin ,  Andy Tsen ,  Jui-Long Chen ,  Sunny Wu ,  Jong-I Mou ,  Chia-Hung Huang

IPC分类号： G06Q10/00 ,  G06F17/18

CPC分类号： G06Q10/06 ,  G06Q30/0202

摘要： A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

摘要翻译： 公开了一种用于在集成电路器件制造工艺的早期阶段提供容量比预测的方法。 该方法包括从一个或多个处理的晶片批次收集历史数据; 从一个或多个偏斜晶片批量收集测量数据; 从收集的历史数据和收集的测量数据生成估计的基线分布; 基于一个或多个指定参数和所生成的估计基线分布产生估计的性能分布; 通过对所生成的估计性能分布应用仓定义和产量退化因子估计来确定仓比预测; 根据仓比预测确定一个或多个生产目标; 以及基于所述一个或多个确定的生产目标来处理一个或多个晶圆。

公开(公告)号：US08946737B2

公开(公告)日：2015-02-03

申请号：US13570214

申请日：2012-08-08

申请人： Ya-Wen Lin ,  Po-Min Tu ,  Shih-Cheng Huang ,  Chia-Hung Huang ,  Shun-Kuei Yang

发明人： Ya-Wen Lin ,  Po-Min Tu ,  Shih-Cheng Huang ,  Chia-Hung Huang ,  Shun-Kuei Yang

IPC分类号： H01L33/00

CPC分类号： H01L33/22 ,  H01L33/007

摘要： A light emitting diode (LED) includes a substrate, a buffer layer and an epitaxial structure. The substrate has a first surface with a patterning structure formed thereon. The patterning structure includes a plurality of projections. The buffer layer is arranged on the first surface of the substrate. The epitaxial structure is arranged on the buffer layer. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer arranged on the buffer layer in sequence. The first semiconductor layer has a second surface attached to the active layer. A distance between a peak of each the projections and the second surface of the first semiconductor layer is ranged from 0.5 μm to 2.5 μm.

摘要翻译： 发光二极管（LED）包括衬底，缓冲层和外延结构。 衬底具有形成在其上的图案化结构的第一表面。 图案形成结构包括多个突起。 缓冲层布置在基板的第一表面上。 外延结构布置在缓冲层上。 外延结构包括顺序地布置在缓冲层上的第一半导体层，有源层和第二半导体层。 第一半导体层具有附着到有源层的第二表面。 每个突起的峰值与第一半导体层的第二表面之间的距离为0.5μm至2.5μm。

公开(公告)号：US08349742B2

公开(公告)日：2013-01-08

申请号：US13013825

申请日：2011-01-26

申请人： Po-Min Tu ,  Shih-Cheng Huang ,  Shun-Kuei Yang ,  Chia-Hung Huang

发明人： Po-Min Tu ,  Shih-Cheng Huang ,  Shun-Kuei Yang ,  Chia-Hung Huang

IPC分类号： H01L21/00

CPC分类号： H01L29/2003 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0254 ,  H01L21/02658 ,  H01L29/16

摘要： A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

摘要翻译： 氮化镓系半导体器件包括复合衬底和氮化镓层。 复合衬底包括硅衬底和填料。 硅衬底包括第一表面和与第一表面相对的第二表面，并且第一表面在其中限定多个凹槽。 将填料填充到硅衬底的第一表面上的槽数中。 填料的热膨胀系数大于硅衬底的热膨胀系数。 氮化镓层形成在硅衬底的第二表面上。

公开(公告)号：US5732536A

公开(公告)日：1998-03-31

申请号：US739072

申请日：1996-10-28

申请人： Ching-Lin Lin ,  Chia-Hung Huang ,  Do-Yu Lee

发明人： Ching-Lin Lin ,  Chia-Hung Huang ,  Do-Yu Lee

IPC分类号： B65B5/10 ,  B65B35/30

CPC分类号： B65B5/106

摘要： A tape roll in-series package machine for neatly packing a plurality of tape rolls into a paper box. In includes (a) a conveying device, (b) an in-series filling device, and (c) a paper box elevating device. The in-series filling device contains first, second, and third pneumatic cylinder each of which is connected to a receiving plate to cooperatively pack a row of the tape rolls into a paper box. The paper elevating device contains (i) a paper box conveyor which is divided into front section, middle and rear sections, each of the sections is driven by a separate mechanism; (ii) an elevating frame disposed above the middle section of the paper box conveyor, wherein the elevating frame contains a pair of fending plates each being driven by a revolving pneumatic cylinder for holding the paper box in place and facilitating the incoming and outgoing motions of the paper box; and (iii) a Z-axis stepping motor which is provided to control an up-and-down motion of the elevating frame so as to adjust a vertical position of the paper box.

摘要翻译： 一种用于将多个带卷整齐地包装在纸盒中的胶带卷筒式包装机。 包括（a）输送装置，（b）串联充填装置，和（c）纸盒升降装置。 串联式灌装装置包括第一，第二和第三气缸，每个气缸连接到接收板，以将一排带卷协同地包装在纸盒中。 纸张升降装置包括：（i）纸箱输送机，其分为前段，中间和后段，每个区段由单独的机构驱动; （ii）设置在纸箱输送机的中间部分上方的升降框架，其中升降架包括一对防火板，每个挡板由用于将纸盒保持在适当位置的旋转气动缸驱动，并且有利于进入和离开运动 纸盒; 和（iii）Z轴步进电机，其被设置为控制升降框架的上下运动，以调节纸盒的垂直位置。

公开(公告)号：US20150265917A1

公开(公告)日：2015-09-24

申请号：US14220150

申请日：2014-03-20

申请人： Chia-Han Chang ,  Chia-Hung Huang ,  Mark Junren Wiener

发明人： Chia-Han Chang ,  Chia-Hung Huang ,  Mark Junren Wiener

IPC分类号： A63F13/31 ,  A63F13/215 ,  A63F13/213 ,  A63F13/212 ,  A63F13/217

CPC分类号： F41J5/04 ,  F41J5/00 ,  F42B12/365 ,  F42B12/40 ,  F42B30/006

摘要： A game apparatus having an attack apparatus, a wearable apparatus and a communication apparatus is provided. The communication apparatus determines a property of the attack apparatus according to an attack signal sensed by the wearable apparatus and adjusts a status prompt signal emitted by the wearable apparatus according to the property of the attack apparatus.

摘要翻译： 提供具有攻击装置，可穿戴装置和通信装置的游戏装置。 通信装置根据由可穿戴装置感测到的攻击信号来确定攻击装置的属性，并根据攻击装置的属性调整由可穿戴装置发出的状态提示信号。

公开(公告)号：US08501582B2

公开(公告)日：2013-08-06

申请号：US12975235

申请日：2010-12-21

申请人： Shih-Cheng Huang ,  Po-Min Tu ,  Shun-Kuei Yang ,  Chia-Hung Huang

发明人： Shih-Cheng Huang ,  Po-Min Tu ,  Shun-Kuei Yang ,  Chia-Hung Huang

IPC分类号： H01L21/76

CPC分类号： H01L29/06 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02614 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/12 ,  H01L33/20

摘要： A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. A method for manufacturing the semiconductor structure is also disclosed.

摘要翻译： 半导体结构包括Si衬底，支撑层和形成在衬底上的阻挡层和形成在支撑层上的外延层。 支撑层在其中限定多个凹槽以接收阻挡层。 外延层从支撑层生长。 在外延层中和阻挡层上限定多个槽。 外延层包括N型半导体层，发光层和P型半导体层。 还公开了半导体结构的制造方法。

公开(公告)号：US08492304B2

公开(公告)日：2013-07-23

申请号：US12650102

申请日：2009-12-30

申请人： Weng-Sing Hwang ,  Shyh-Jiun Liu ,  Chia-Hung Huang ,  Chun-Kai Huang

发明人： Weng-Sing Hwang ,  Shyh-Jiun Liu ,  Chia-Hung Huang ,  Chun-Kai Huang

IPC分类号： B01J31/12 ,  B01J23/745 ,  C01G49/08

CPC分类号： B01J37/086 ,  B01J21/18 ,  B01J23/745 ,  B01J31/1805 ,  B01J31/1815 ,  B01J35/002 ,  B01J35/006 ,  B01J2531/842 ,  B82Y30/00 ,  C01G49/08 ,  C01P2002/72 ,  C01P2004/04 ,  C01P2004/64 ,  C01P2006/40 ,  C07F15/025 ,  H01M4/9016 ,  H01M4/9083 ,  H01M2008/1095

摘要： A manufacturing method of an iron complex is mixing ferric chloride and at least one chelating agent with a solvent, wherein Fe3+ ions of ferric chloride is reacted with the at least one chelating agent to form an iron complex Fe[R1]a[R2]b[H2O]c3+ or Fe[R1]a[H2O]c3+, wherein the at least one chelating agent is selected from a group including ethylenediamine, 1,10-phenanthroline, 2,2′-Bipyridine, diethylenetriamine, triethylenetetraamine, phenanthroline, or bipyridine. Moreover, a method for producing an iron oxide catalyst is mixing ferric chloride, at least one chelating agent and the support with a solvent to form an iron complex, which is incorporated with the support. Following, a drying step and a heat treatment step are processed to get the iron oxide catalyst.

摘要翻译： 铁络合物的制造方法是将氯化铁和至少一种螯合剂与溶剂混合，其中氯化铁的Fe 3+离子与至少一种螯合剂反应形成铁络合物Fe [R1] a [R2] b [H2O] c3 +或Fe [R1] a [H2O] c3 +，其中所述至少一种螯合剂选自包括乙二胺，1,10-菲咯啉，2,2'-联吡啶，二亚乙基三胺，三亚乙基四胺，菲咯啉或 联吡啶。 此外，氧化铁催化剂的制造方法是将氯化铁，至少一种螯合剂和载体与溶剂混合，形成配合了载体的铁络合物。 接着，对干燥工序和热处理工序进行处理，得到氧化铁催化剂。

公开(公告)号：US08461619B2

公开(公告)日：2013-06-11

申请号：US13397688

申请日：2012-02-16

申请人： Chia-Hung Huang ,  Shih-Cheng Huang ,  Po-Min Tu ,  Shun-Kuei Yang

发明人： Chia-Hung Huang ,  Shih-Cheng Huang ,  Po-Min Tu ,  Shun-Kuei Yang

IPC分类号： H01L33/36

CPC分类号： H01L33/38 ,  H01L33/14 ,  H01L33/20 ,  H01L33/42 ,  H01L2933/0016

摘要： An LED chip includes a substrate, a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first electrode and a second electrode formed on the substrate in sequence. A surface of the first type semiconductor layer away from the substrate comprises an exposed first area and a second area covered by the light-emitting layer. The first electrode is formed on the exposed first area of the substrate. A number of recesses are defined in the second area of the surface of the first type semiconductor layer. The recesses are spaced apart from each other and arranged in sequence in a direction away from the first electrode; depths of the recesses gradually decrease following an increase of a distance between the recesses and the first electrode. The second electrode is formed on the second type semiconductor layer.

摘要翻译： LED芯片依次包括基板，第一类型半导体层，发光层，第二类型半导体层，第一电极和第二电极。 离开衬底的第一类型半导体层的表面包括暴露的第一区域和被发光层覆盖的第二区域。 第一电极形成在基板的暴露的第一区域上。 在第一类型半导体层的表面的第二区域中限定多个凹部。 凹部彼此间隔开并且沿远离第一电极的方向依次布置; 随着凹部和第一电极之间的距离的增加，凹部的深度逐渐减小。 第二电极形成在第二类型半导体层上。

公开(公告)号：US08450749B2

公开(公告)日：2013-05-28

申请号：US12986186

申请日：2011-01-07

申请人： Po-Min Tu ,  Shih-Cheng Huang ,  Shun-Kuei Yang ,  Chia-Hung Huang

发明人： Po-Min Tu ,  Shih-Cheng Huang ,  Shun-Kuei Yang ,  Chia-Hung Huang

IPC分类号： H01L33/30 ,  H01L33/44

CPC分类号： H01L33/12 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02661 ,  H01L33/007

摘要： A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween.

摘要翻译： 发光元件包括衬底，形成在衬底上的GaN层，形成在GaN层上的第一低折射率半导体层和形成在第一低折射率半导体层上的具有高折射率的点亮结构。 第二低折射率半导体层嵌入在第一低折射率半导体层中。 第一低折射率半导体层和GaN层之间呈现晶格失配。