公开(公告)号：US20160080865A1

公开(公告)日：2016-03-17

申请号：US14507372

申请日：2014-10-06

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson

IPC: H04R3/04 ,  H03G3/00

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

Abstract translation: 根据本公开的实施例，控制电路可以被配置为响应于在具有模拟路径部分的信号路径的增益模式和数字信号路径部分之间切换的指示，切换模拟的可选择的模拟增益 在第一模拟增益和第二模拟增益之​​间的路径部分，在第一数字增益和第二数字增益之间切换数字信号路径部分的可选数字增益，其中第一模拟增益和第一数字增益的乘积近似 等于第二模拟增益和第二数字增益的乘积，并且作为信号路径的增益模式之间的切换的结果，控制信号路径的模拟响应以减少存在于输出信号中的音频伪像的出现。 信号路径可以具有模拟路径部分和数字信号路径部分。 数字部分可以具有可选择的数字控制的增益，并且可以被配置为将数字音频输入信号转换成符合可选数字控制的增益的模拟输入信号，数字信号路径部分包括调制器，包括前向路径和 反馈路径。 正向路径可以包括环路滤波器，用于响应于数字音频输入信号和反馈信号产生经滤波的信号，响应于经滤波的信号产生量化信号的量化器，以及第一增益元件，被配置为将可选择的数字 - 控制增益到正向路径内的信号。 反馈路径可以被配置为响应于量化信号产生反馈信号，反馈路径包括具有与可选数字控制增益成反比的增益的第二增益元件。

公开(公告)号：US09258001B1

公开(公告)日：2016-02-09

申请号：US14016972

申请日：2013-09-03

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Alvin C. Storvik

IPC: H03L7/087 ,  H03L7/093 ,  H03L7/14 ,  H03L7/10 ,  H03L7/107

CPC classification number: H03L7/148 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/103 ,  H03L7/105 ,  H03L7/1075 ,  H03L7/146 ,  H03L7/18 ,  H03L7/22 ,  H03L2207/06

Abstract: An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.

Abstract translation: 锁相环（PLL）或锁频环（FLL）的振荡器可以包括两个输入。 两个输入可以包括第一模拟输入和第二数字输入。 第二数字输入可以接收设置振荡器的期望输出时钟频率的数字信号和/或指示振荡器输出的频率范围的近似频率。 第一模拟输入可以接收代表PLL或FLL的输出时钟频率的期望频率的电压，以从由第二数字输入设置的近似频率微调输出频率。 第一模拟输入可以从主时钟输入信号产生。 当主时钟输入信号消失时，即使没有主时钟输入信号，第二数字信号控制振荡器的输出频率，以允许PLL或FLL的冗余操作。

公开(公告)号：US20150295584A1

公开(公告)日：2015-10-15

申请号：US14680830

申请日：2015-04-07

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  John L. Melanson ,  John C. Tucker ,  Xiaofan Fei

IPC: H03M1/00 ,  H03M1/70 ,  H03M1/66 ,  H03M1/08 ,  H03M1/78

CPC classification number: H03M1/002 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/662 ,  H03M1/68 ,  H03M1/70 ,  H03M1/785 ,  H03M3/32 ,  H03M3/392 ,  H03M3/414 ,  H03M3/416 ,  H03M3/50

Abstract: In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.

Abstract translation: 根据本公开的实施例，处理系统可以包括多个处理路径，包括第一处理路径和第二处理路径，数模转换阶段输出和控制器。 第一处理路径可以包括用于将数字输入信号转换成第一中间模拟信号的第一数模转换器，第一数模转换器被配置为在大功率状态和低功率状态 。 第二处理路径可以包括用于将数字输入信号转换成第二中间模拟信号的第二数模转换器。 数模转换级输出可以被配置为产生包括第一中间模拟信号和第二中间模拟信号之和的模拟信号。 控制器可以被配置为当数字输入信号的幅度低于阈值幅度时，在较低功率状态下操作第一数模转换器。

公开(公告)号：US09998823B2

公开(公告)日：2018-06-12

申请号：US14507372

申请日：2014-10-06

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson ,  Anniruddha Satoskar

IPC: H04R3/00 ,  H03G3/20 ,  H03G3/00 ,  H04R3/04 ,  H03G3/30 ,  H03G9/00

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

公开(公告)号：US09648414B1

公开(公告)日：2017-05-09

申请号：US14169946

申请日：2014-01-31

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Daniel John Allen

IPC: H04R3/00 ,  H03G3/00 ,  G06F1/00 ,  H04M3/00 ,  H04R1/40 ,  H03K3/00 ,  G11B20/14 ,  G06F13/42 ,  G11B20/10

CPC classification number: H04R3/00 ,  G06F1/00 ,  G06F13/42 ,  G11B20/10527 ,  G11B20/1403 ,  H03G3/00 ,  H03G3/348 ,  H03K3/00 ,  H04M3/002 ,  H04R1/403 ,  H04R1/406 ,  Y02D10/14 ,  Y02D10/151

Abstract: Responsive to the absence of a reference clock input signal to a clock conditioning circuit for generating a desired clock signal for synchronizing components of an audio signal path, a controller may cause the signal path to receive at the clock input a substitute clock signal in the absence of the reference clock input signal and may modify one or more parameters of the signal path in order to perform one or more of the following: (i) reduce the presence of audio artifacts in the output signal caused by the absence of the reference clock input signal; (ii) power down at least one component of the signal path to reduce power consumed by the signal path; (iii) continue to operate the signal path with the substitute clock signal; and (iv) transition the signal path to a mute condition or a zero volume condition.

公开(公告)号：US09596537B2

公开(公告)日：2017-03-14

申请号：US14483659

申请日：2014-09-11

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson ,  Aniruddha Satoskar

IPC: H03G3/00 ,  H04R3/00 ,  H03G3/20 ,  H04R3/04 ,  H03G3/30 ,  H03F99/00

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

Abstract translation: 信号路径可以具有模拟路径部分和数字信号路径部分。 数字部分可以具有可选择的数字控制的增益，并且可以被配置为将数字音频输入信号转换成符合可选数字控制的增益的模拟输入信号，数字信号路径部分包括调制器，包括前向路径和 反馈路径。 正向路径可以包括环路滤波器，用于响应于数字音频输入信号和反馈信号产生经滤波的信号，响应于经滤波的信号产生量化信号的量化器，以及第一增益元件，被配置为将可选择的数字 - 控制增益到正向路径内的信号。 反馈路径可以被配置为响应于量化信号产生反馈信号，反馈路径包括具有与可选数字控制增益成反比的增益的第二增益元件。

公开(公告)号：US20160072465A1

公开(公告)日：2016-03-10

申请号：US14481201

申请日：2014-09-09

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Xin Zhao ,  Ted Burk ,  Ku He ,  John L. Melanson ,  Xiaofan Fei

IPC: H03G3/20 ,  H03G3/00

CPC classification number: H03G3/20 ,  H03G3/001 ,  H03G3/002 ,  H03G3/3005 ,  H03G3/3089

Abstract: A signal path may operate in one of a plurality of gain modes such that for each gain mode, the product of a digital gain and an analog signal gain of the signal path associated with the particular gain mode are approximately equal to a fixed path gain. During each of one or more calibration phases, a calibration system may measure analog signals at a plurality of nodes of the first path portion, calculate an actual analog gain associated with the gain mode based on the analog signals measured at the plurality of nodes, calculate an error between the fixed path gain and a mathematical product of the actual analog gain associated with the gain mode and the digital gain associated with the gain mode, and modify at least one of the digital gain and the analog gain associated with the gain mode in conformity with the error.

Abstract translation: 信号路径可以以多种增益模式之一操作，使得对于每个增益模式，与特定增益模式相关联的信号路径的数字增益和模拟信号增益的乘积近似等于固定路径增益。 在一个或多个校准阶段的每一个期间，校准系统可以测量第一路径部分的多个节点处的模拟信号，基于在多个节点处测量的模拟信号来计算与增益模式相关联的实际模拟增益，计算 固定路径增益与与增益模式相关联的实际模拟增益与与增益模式相关联的数字增益的数学乘积之间的误差，并且修改与增益模式相关联的数字增益和模拟增益中的至少一个 符合错误。

公开(公告)号：US10785568B2

公开(公告)日：2020-09-22

申请号：US14467969

申请日：2014-08-25

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Ku He ,  John L. Melanson

IPC: H04R3/02 ,  H03M1/70 ,  H03G3/30 ,  H03G3/00

Abstract: In accordance with embodiments of the present disclosure, an apparatus for providing an output signal to an audio transducer may include a control circuit. The control circuit may be configured to predict, based on a magnitude of a signal indicative of the output signal, an occurrence of an event for changing a selectable digital gain and a selectable analog gain and an audio signal path, and responsive to predicting the occurrence of the event, change, at an approximate time in which a zero crossing of the signal indicative of the output signal occurs, the selectable digital gain and the selectable analog gain.

公开(公告)号：US09584911B2

公开(公告)日：2017-02-28

申请号：US14975015

申请日：2015-12-18

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  John L. Melanson

IPC: H03M1/00 ,  H04R3/04 ,  H03G7/00 ,  H03G9/00 ,  H03M1/12 ,  H04L1/20 ,  H04L27/26

CPC classification number: H04R3/04 ,  G10L19/167 ,  G10L21/0324 ,  H03G7/007 ,  H03G9/005 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/18 ,  H03M2201/4135 ,  H04L1/20 ,  H04L27/2647 ,  H04R2430/01 ,  H04R2430/03

Abstract: In accordance with embodiments of the present disclosure, a multichip circuit for processing audio signals having dynamic range enhancement information over two or more integrated circuits may include a host integrated circuit and a client integrated circuit. The host integrated circuit may be configured to determine a dynamic range enhancement gain for a digital audio input signal, process the digital audio input signal in accordance with the dynamic range enhancement gain, and transmit audio data based on the processed digital audio input signal. The client integrated circuit may be coupled to the host integrated circuit and may be configured to receive the audio data and wherein the client integrated circuit is provided with the dynamic range enhancement gain and the client integrated circuit is configured to process the audio data with the dynamic range enhancement gain.

Abstract translation: 根据本公开的实施例，用于处理在两个或多个集成电路上具有动态范围增强信息的音频信号的多芯片电路可以包括主机集成电路和客户端集成电路。 主机集成电路可以被配置为确定用于数字音频输入信号的动态范围增强增益，根据动态范围增强增益处理数字音频输入信号，并且基于处理的数字音频输入信号发送音频数据。 客户端集成电路可以耦合到主机集成电路，并且可以被配置为接收音频数据，并且其中向客户端集成电路提供动态范围增强增益，并且客户端集成电路被配置为使用动态范围处理音频数据 范围增强增益。

公开(公告)号：US20160286310A1

公开(公告)日：2016-09-29

申请号：US14975015

申请日：2015-12-18

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  John L. Melanson

IPC: H04R3/04

CPC classification number: H04R3/04 ,  G10L19/167 ,  G10L21/0324 ,  H03G7/007 ,  H03G9/005 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/18 ,  H03M2201/4135 ,  H04L1/20 ,  H04L27/2647 ,  H04R2430/01 ,  H04R2430/03

Abstract: In accordance with embodiments of the present disclosure, a multichip circuit for processing audio signals having dynamic range enhancement information over two or more integrated circuits may include a host integrated circuit and a client integrated circuit. The host integrated circuit may be configured to determine a dynamic range enhancement gain for a digital audio input signal, process the digital audio input signal in accordance with the dynamic range enhancement gain, and transmit audio data based on the processed digital audio input signal. The client integrated circuit may be coupled to the host integrated circuit and may be configured to receive the audio data and wherein the client integrated circuit is provided with the dynamic range enhancement gain and the client integrated circuit is configured to process the audio data with the dynamic range enhancement gain.

Abstract translation: 根据本公开的实施例，用于处理在两个或多个集成电路上具有动态范围增强信息的音频信号的多芯片电路可以包括主机集成电路和客户端集成电路。 主机集成电路可以被配置为确定用于数字音频输入信号的动态范围增强增益，根据动态范围增强增益处理数字音频输入信号，并且基于处理的数字音频输入信号发送音频数据。 客户端集成电路可以耦合到主机集成电路，并且可以被配置为接收音频数据，并且其中向客户端集成电路提供动态范围增强增益，并且客户端集成电路被配置为使用动态范围处理音频数据 范围增强增益。