公开(公告)号：US10714616B2

公开(公告)日：2020-07-14

申请号：US15678206

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/762

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

公开(公告)号：US10056408B2

公开(公告)日：2018-08-21

申请号：US15335549

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

公开(公告)号：US09525069B2

公开(公告)日：2016-12-20

申请号：US14576611

申请日：2014-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US09548306B2

公开(公告)日：2017-01-17

申请号：US15144924

申请日：2016-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Andres Bryant ,  Tenko Yamashita

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/45

Abstract: In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

Abstract translation: 在形成半导体结构的方法中，介电层的不同部分在处理期间在不同的阶段被蚀刻，以形成用于第一FET（例如，NFET）的第一栅极侧壁间隔件和用于第二FET的第二栅极侧壁间隔物 例如PFET），使得第一和第二栅极侧壁间隔物是对称的。 在第一栅极侧壁间隔物形成之后立即形成用于第一FET的升高的源极/漏极区，并且在第二栅极侧壁间隔物形成之后立即形成用于第二FET的升高的源极/漏极区。 由于两个FET的栅极侧壁间隔物是对称的，所以两个FET的源极/漏极结也将是对称的。 另外，由于形成在第一FET的升高的源极/漏极区上而不是第二FET的蚀刻停止层，不同的FET的升高的源极/漏极区上的不同的金属硅化物。

公开(公告)号：US20180012988A1

公开(公告)日：2018-01-11

申请号：US15678206

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3115 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

公开(公告)号：US09673055B2

公开(公告)日：2017-06-06

申请号：US14613416

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211

Abstract: A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.

公开(公告)号：US20160380100A1

公开(公告)日：2016-12-29

申请号：US14751557

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Edward J. Nowak ,  Robert R. Robison

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/845 ,  G05F3/16 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/78696

Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

Abstract translation: 一种具有参考装置的集成电路及其形成方法。 公开了一种参考装置，其具有：实现为具有基本上未掺杂主体的长通道装置的完全耗尽的n型MOSFET; 以及用作具有基本上未掺杂的主体的长沟道器件实现的完全耗尽的p型MOSFET; 其中所述n型MOSFET和p型MOSFET串联连接并采用相同的栅极叠层，其中每个都具有电耦合到相应漏极的栅极以形成两个二极管，并且其中两个二极管处于导通状态和 根据施加在n型MOSFET和p型MOSFET上的电位的值的关闭状态。

公开(公告)号：US09478615B2

公开(公告)日：2016-10-25

申请号：US14493749

申请日：2014-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/36 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/1041 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28026 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract translation: 一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。 此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

公开(公告)号：US20160247805A1

公开(公告)日：2016-08-25

申请号：US15144924

申请日：2016-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Andres Bryant ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/45

Abstract: In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

Abstract translation: 在形成半导体结构的方法中，介电层的不同部分在处理期间在不同的阶段被蚀刻，以形成用于第一FET（例如，NFET）的第一栅极侧壁间隔件和用于第二FET的第二栅极侧壁间隔物 例如PFET），使得第一和第二栅极侧壁间隔物是对称的。 在第一栅极侧壁间隔物形成之后立即形成用于第一FET的升高的源极/漏极区，并且在第二栅极侧壁间隔物形成之后立即形成用于第二FET的升高的源极/漏极区。 由于两个FET的栅极侧壁间隔物是对称的，所以两个FET的源极/漏极结也将是对称的。 另外，由于形成在第一FET的升高的源极/漏极区上而不是第二FET的蚀刻停止层，不同的FET的升高的源极/漏极区上的不同的金属硅化物。

公开(公告)号：US09805990B2

公开(公告)日：2017-10-31

申请号：US14751557

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Edward J. Nowak ,  Robert R. Robison

IPC: H01L21/84 ,  G05F3/16 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/845 ,  G05F3/16 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/78696

Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.