公开(公告)号：US20170141110A1

公开(公告)日：2017-05-18

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US20150168824A1

公开(公告)日：2015-06-18

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei SUN ,  Chanro PARK ,  Wenhui WANG ,  Hui ZANG

IPC: G03F1/62 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。

公开(公告)号：US20180096839A1

公开(公告)日：2018-04-05

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han KIM ,  Wenhui WANG ,  Azat LATYPOV ,  Tamer COSKUN ,  Lei SUN

IPC: H01L21/027 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481 ,  H01L22/12 ,  H01L22/30

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

公开(公告)号：US20190113836A1

公开(公告)日：2019-04-18

申请号：US15784408

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei SUN ,  Obert R. WOOD, II ,  Genevieve BEIQUE ,  Yulu CHEN ,  Erik VERDUIJN ,  Francis GOODWIN

IPC: G03F1/24 ,  G03F1/58 ,  G03F1/80

CPC classification number: G03F1/24 ,  G03F1/58 ,  G03F1/80

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an extreme ultraviolet (EUV) lithography mask and methods of manufacture. The EUV mask structure includes: a reflective layer; a capping material on the reflective layer; a buffer layer on the capping layer; alternating absorber layers on the buffer layer; and a capping layer on the top of the alternating absorber layers.

公开(公告)号：US20160365288A1

公开(公告)日：2016-12-15

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L21/8238 ,  H01L23/528 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20180144976A1

公开(公告)日：2018-05-24

申请号：US15360255

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng LAW ,  Xunyuan ZHANG ,  Frank W. MONT ,  Genevieve BEIQUE ,  Lei SUN

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76816 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76877 ,  H01L23/5283

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.

公开(公告)号：US20160223896A1

公开(公告)日：2016-08-04

申请号：US14609588

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei SUN ,  Obert Reeves WOOD, II

IPC: G03F1/22

CPC classification number: G03F1/22 ,  G03F1/24 ,  G03F1/58

Abstract: Methods for creating a EUV photolithography mask with a thinner highly EUV absorbing absorber layer and the resulting device are disclosed. Embodiments include forming a multilayer reflector (MLR); forming first and second layers of a first EUV absorbing material over the MLR, the second layer being between the first layer and the MLR; and implanting the first layer with particles of a second EUV absorbing material, wherein the first EUV absorbing material is etchable and has a lower EUV absorption coefficient than the second EUV absorbing material, and wherein the implanted particles are substantially separated from each other.

Abstract translation: 公开了用于制造具有较薄的高度EUV吸收层的EUV光刻掩模和所得到的器件的方法。 实施例包括形成多层反射器（MLR）; 在所述MLR上形成第一EUV吸收材料的第一层和第二层，所述第二层位于所述第一层和所述MLR之间; 以及用第二EUV吸收材料的颗粒注入所述第一层，其中所述第一EUV吸收材料是可蚀刻的并且具有比所述第二EUV吸收材料更低的EUV吸收系数，并且其中所述注入的颗粒彼此基本上分离。