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    HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE
    3.
    发明申请
    HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE 有权
    具有降低电容性能的高性能热风炉

    公开(公告)号：US20160379999A1

    公开(公告)日：2016-12-29

    申请号：US14748355

    申请日：2015-06-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anthony I. Chou ,  Sungjae Lee ,  Joseph M. Lukaitis ,  Robert R. Robison

    IPC: H01L27/12 ,  H01L21/3205 ,  H01L21/22 ,  H01L23/522 ,  H01L23/373

    CPC classification number: H01L27/1207 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/535

    Abstract: Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.

    Abstract translation: 将隔热层与绝缘体上硅衬底的处理晶片电容性隔离的方法和结构。 接触插塞位于延伸穿过绝缘体上硅衬底的器件层中的沟槽隔离区域并且至少部分地穿过绝缘体上硅衬底的掩埋绝缘体层的沟槽中。 隔热罩位于互连结构中，其还包括将隔热罩与接触插头连接的线。 隔离结构位于接触塞和处理晶片的一部分之间。 隔离结构提供电容隔离。

    High performance heat shields with reduced capacitance
    4.
    发明授权
    High performance heat shields with reduced capacitance 有权
    具有降低电容的高性能隔热罩

    公开(公告)号：US09530798B1

    公开(公告)日：2016-12-27

    申请号：US14748355

    申请日：2015-06-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anthony I. Chou ,  Sungjae Lee ,  Joseph M. Lukaitis ,  Robert R. Robison

    IPC: H01L23/552 ,  H01L23/66 ,  H01L27/12 ,  H01L23/522 ,  H01L23/373 ,  H01L21/22 ,  H01L21/3205

    CPC classification number: H01L27/1207 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/535

    Abstract: Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.

    Abstract translation: 将隔热层与绝缘体上硅衬底的处理晶片电容性隔离的方法和结构。 接触插塞位于延伸穿过绝缘体上硅衬底的器件层中的沟槽隔离区域并且至少部分地穿过绝缘体上硅衬底的掩埋绝缘体层的沟槽中。 隔热罩位于互连结构中，其还包括将隔热罩与接触插头连接的线。 隔离结构位于接触塞和处理晶片的一部分之间。 隔离结构提供电容隔离。

    Buried signal transmission line
    5.
    发明授权
    Buried signal transmission line 有权
    埋地信号传输线

    公开(公告)号：US09484246B2

    公开(公告)日：2016-11-01

    申请号：US14307604

    申请日：2014-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee ,  Richard A. Wachnik

    IPC: H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L21/74 ,  H01L27/12

    CPC classification number: H01L21/76283 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit.

    Abstract translation: 在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成掩埋导电层。 形成横向围绕埋入导电层的一部分的深隔离沟槽，并且至少填充有介电衬垫以形成深电容器沟槽隔离结构。 通过结构的接触通过掩埋绝缘体层和顶部半导体层形成，并且形成在掩埋导电层的构成掩埋导电导管的部分上。 深电容器沟槽隔离结构可以与至少一个深沟槽电容器同时形成。 可以使用顶部半导体层的图案化部分作为用于信号传输的附加导电管道。 此外，深电容器沟槽隔离结构可以包括导电部分，导电部分可被电偏置以控制包括埋入导电导管的信号路径的阻抗。

    CMOS GATE CONTACT RESISTANCE REDUCTION
    6.
    发明申请
    CMOS GATE CONTACT RESISTANCE REDUCTION 有权
    CMOS栅极接触电阻降低

    公开(公告)号：US20160172378A1

    公开(公告)日：2016-06-16

    申请号：US14566779

    申请日：2014-12-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

    IPC: H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L27/1211 ,  H01L21/28017 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653

    Abstract: A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.

    Abstract translation: 通过增加栅极接触和栅极结构的栅极导电部分之间的接触面积来提供具有降低的接触电阻的栅极接触。 栅极接触形成与栅极导电部分的一部分的最顶表面和最外侧壁的至少部分的直接接触，从而增加了栅极接触和栅极结构之间的接触面积。 通过用栅极接触完全围绕栅极结构的栅极导电部分的一部分，可以进一步提高本申请的栅极接触面积。

    CMOS gate contact resistance reduction
    10.
    发明授权
    CMOS gate contact resistance reduction 有权
    CMOS栅极接触电阻降低

    公开(公告)号：US09412759B2

    公开(公告)日：2016-08-09

    申请号：US14566779

    申请日：2014-12-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

    IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311 ,  H01L21/84 ,  H01L21/28

    CPC classification number: H01L27/1211 ,  H01L21/28017 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653

    Abstract: A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.

    Abstract translation: 通过增加栅极接触和栅极结构的栅极导电部分之间的接触面积来提供具有降低的接触电阻的栅极接触。 栅极接触形成与栅极导电部分的一部分的最顶表面和最外侧壁的至少部分的直接接触，从而增加了栅极接触和栅极结构之间的接触面积。 通过用栅极接触完全围绕栅极结构的栅极导电部分的一部分，可以进一步提高本申请的栅极接触面积。

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